TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) Reference Guide

TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI)

Reference Guide

Literature Number: SPRUG71B February 2009 – Revised October 2009

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Preface ....................................................................................................................................... 6 1 Enhanced SPI Module Overview ............................................................................................ 8

..................................................................................................... 10 ......................................................................................... 11 1.3 Overview of SPI Module Registers .................................................................................. 11 1.4 SPI Operation .......................................................................................................... 12 1.5 SPI Interrupts ........................................................................................................... 14 1.6 SPI FIFO Description .................................................................................................. 19 1.7 SPI 3-Wire Mode Description ........................................................................................ 21 1.8 SPI STEINV Bit in Digital Audio Transfers ......................................................................... 24 2 SPI Registers and Waveforms ............................................................................................. 25 2.1 SPI Control Registers ................................................................................................. 25 2.2 SPI Example Waveforms ............................................................................................. 35 Appendix A Revision History ...................................................................................................... 38
1.1 1.2 SPI Block Diagram SPI Module Signal Summary

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Table of Contents

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List of Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SPI CPU Interface .......................................................................................................... 8 Serial Peripheral Interface Module Block Diagram.................................................................... 10 SPI Master/Slave Connection ............................................................................................ 13 SPICLK Signal Options ................................................................................................... 17 SPI: SPICLK-CLKOUT Characteristic When (BRR + 1) is Odd, BRR > 3, and CLOCK POLARITY = 1 ...... 17 Five Bits per Character ................................................................................................... 19

............................................................. SPI 3-wire Master Mode .................................................................................................. SPI 3-wire Slave Mode ................................................................................................... SPI Digital Audio Receiver Configuration Using 2 SPIs .............................................................. Standard Right-Justified Digital Audio Data Format .................................................................. SPI Configuration Control Register (SPICCR) — Address 7040h .................................................. SPI Operation Control Register (SPICTL) — Address 7041h ....................................................... SPI Status Register (SPIST) — Address 7042h ...................................................................... SPI Baud Rate Register (SPIBRR) — Address 7044h ............................................................... SPI Emulation Buffer Register (SPIRXEMU) — Address 7046h .................................................... SPI Serial Receive Buffer Register (SPIRXBUF) — Address 7047h ............................................... SPI Serial Transmit Buffer Register (SPITXBUF) — Address 7048h .............................................. SPI Serial Data Register (SPIDAT) — Address 7049h ............................................................... SPI FIFO Transmit (SPIFFTX) Register Address 704Ah .......................................................... SPI FIFO Receive (SPIFFRX) Register Address 704Bh........................................................... SPI FIFO Control (SPIFFCT) Register Address 704Ch ............................................................ SPI Priority Control Register (SPIPRI) — Address 704Fh ...........................................................
SPI FIFO Interrupt Flags and Enable Logic Generation

20 22 22 24 24 25 26 27 28 29 29 30 30 31 31 32 34

CLOCK POLARITY = 0, CLOCK PHASE = 0 (All data transitions are during the rising edge, non-delayed clock. Inactive level is low.) .............................................................................................. 35 CLOCK POLARITY = 0, CLOCK PHASE = 1 (All data transitions are during the rising edge, but delayed by half clock cycle. Inactive level is low.)............................................................................... 35 CLOCK POLARITY = 1, CLOCK PHASE = 0 (All data transitions are during the falling edge. Inactive level is high.) ............................................................................................................... 36 CLOCK POLARITY = 1, CLOCK PHASE = 1 (All data transitions are during the falling edge, but delayed by half clock cycle. Inactive level is high.).............................................................................. 36 SPISTE Behavior in Master Mode (Master lowers SPISTE during the entire 16 bits of transmission.)........ 37 SPISTE Behavior in Slave Mode (Slave’s SPISTE is lowered during the entire 16 bits of transmission.) .... 37

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List of Figures

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List of Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SPI Module Signal Summary ............................................................................................ 11

.............................................................................................................. SPI Clocking Scheme Selection Guide ................................................................................. SPI Interrupt Flag Modes ................................................................................................. 4-wire vs. 3-wire SPI Pin Functions ..................................................................................... 3-Wire SPI Pin Configuration ............................................................................................ SPI Configuration Control Register (SPICCR) Field Descriptions .................................................. Character Length Control Bit Values.................................................................................... SPI Operation Control Register (SPICTL) Field Descriptions ....................................................... SPI Status Register (SPIST) Field Descriptions....................................................................... Field Descriptions ......................................................................................................... SPI Emulation Buffer Register (SPIRXEMU) Field Descriptions .................................................... SPI Serial Receive Buffer Register (SPIRXBUF) Field Descriptions ............................................... SPI Serial Transmit Buffer Register (SPITXBUF) Field Descriptions ............................................... SPI Serial Data Register (SPIDAT) Field Descriptions ............................................................... SPI FIFO Transmit (SPIFFTX) Register Field Descriptions ......................................................... SPI FIFO Receive (SPIFFRX) Register Field Descriptions .......................................................... SPI FIFO Control (SPIFFCT) Register Field Descriptions ........................................................... SPI Priority Control Register (SPIPRI) Field Descriptions ........................................................... Changes in Revision A ...................................................................................................
SPI Registers

11 17 20 21 22 25 26 26 27 28 29 29 30 30 31 32 32 34 38

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List of Tables

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Preface
SPRUG71B – February 2009 – Revised October 2009

This guide describes how the serial peripheral interface works on the TMS320x2802x, 2803x Piccolo devices.

About This Manual
The SPI module described in this reference guide is a Type 1 SPI. See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for a list of all devices with an SPI module of the same type, to determine the differences between types, and for a list of device-specific differences within a type.

Related Documentation From Texas Instruments
The following books describe the TMS320x281x and related support tools that are available on the TI website: SPRS523 — TMS320F28020, TMS320F28021, TMS320F28022, TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the 2802x devices. SPRZ292 — TMS320F28020, TMS320F28021, TMS320F28022, TMS320F28023, TMS320F28026, TMS320F28027 Piccolo MCU Silicon Errata describes known advisories on silicon and provides workarounds. SPRS584 — TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 Piccolo Microcontrollers Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the 2803x devices. SPRZ295 — TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 Piccolo MCU Silicon Errata describes known advisories on silicon and provides workarounds. CPU User's Guides— SPRU430 — TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. Peripheral Guides— SPRUFN3 — TMS320x2802x Piccolo System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 2802x microcontrollers (MCUs). SPRUGL8 — TMS320x2803x Piccolo System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 2803x microcontrollers (MCUs). SPRU566 — TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). SPRUGO0 — TMS320x2803x Piccolo Boot ROM Reference Guide describes the purpose and features of the bootloader (factory-programmed boot-loading software) and provides examples of code. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory. SPRUFN6 — TMS320x2802x Piccolo Boot ROM Reference Guide describes the purpose and features of the bootloader (factory-programmed boot-loading software) and provides examples of code. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory.

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Preface

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Trademarks

SPRUGE6 — TMS320x2803x Piccolo Control Law Accelerator (CLA) Reference Guide describes the operation of the Control Law Accelerator (CLA). SPRUGE2 — TMS320x2803x Piccolo Local Interconnect Network (LIN) Module Reference Guide describes the operation of the Local Interconnect Network (LIN) Module. SPRUFK8 — TMS320x2803x Piccolo Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide describes the operation of the Enhanced Quadrature Encoder Pulse (eQEP) module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and position control systems. It includes the module description on registers. SPRUGL7 — TMS320x2803x Piccolo Enhanced Controller Area Network (eCAN) Reference Guide describes the operation of the Enhanced Controller Area Network (eCAN) which uses established protocol to communicate serially with other controllers in electrically noisy environments. SPRUGE5 — TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC. SPRUGE9 — TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion. SPRUGE8 — TMS320x2802x, 2803x Piccolo High-Resolution Pulse Width Modulator (HRPWM) describes the operation of the high-resolution extension to the pulse width modulator (HRPWM). SPRUGH1 — TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) Reference Guide describes how to use the SCI. SPRUFZ8 — TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module Reference Guide describes the enhanced capture module. It includes the module description and registers. SPRUG71 — TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) Reference Guide describes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. SPRUFZ9 — TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) Reference Guide describes the features and operation of the inter-integrated circuit (I2C) module. Tools Guides— SPRU513 — TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. SPRU514 — TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. SPRU608 — TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x core.

Trademarks
Code Composer Studio and C28x are trademarks of Texas Instruments.

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Reference Guide
SPRUG71B – February 2009 – Revised October 2009

Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a high-speed synchronous serial input/ output (I/O) port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the DSP controller and external peripherals or another controller. Typical applications include external I/O or peripheral expansion via devices such as shift registers, display drivers, and analog-to-digital converters (ADCs). Multidevice communications are supported by the master/slave operation of the SPI. On the C28x, the port supports a 4 -level, receive and transmit FIFO for reducing CPU servicing overhead. This reference guide is applicable for the SPI found on the TMS320x2802x and TMS320x2803x families of devices . This includes all Flash-based, ROM-based and RAM-based devices within these families.
NOTE: The 28x SPI features several enhancements compared to the 240xA SPI. See section 1.5 for a description of these features.

1

Enhanced SPI Module Overview
Figure 1 shows the SPI CPU interfaces. Figure 1. SPI CPU Interface
System control block Low speed prescaler SYSCLKOUT CPU

SPIAENCLK

LSPCLK

SYSRS Peripheral Bus SPIINT/RXINT TXINT PIE block
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SPISIMO SPI SPICLK SPISTE Registers SPISOMI GPIO MUX

The SPI module features include: SPISOMI: SPI slave-output/master-input pin SPISIMO: SPI slave-input/master-output pin SPISTE: SPI slave transmit-enable pin
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Enhanced SPI Module Overview



SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.







Two operational modes: master and slave Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the maximum speed of the I/O buffers used on the SPI pins. See the device-specific data sheet for more details. Data word length: one to sixteen data bits Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Simultaneous receive and transmit operation (transmit function can be disabled in software) Transmitter and receiver operations are accomplished through either interrupt- driven or polled algorithms. 12 SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (70), and the upper byte (158) is read as zeros. Writing to the upper byte has no effect.

Enhanced Features: 4-level transmit/receive FIFO Delayed transmit control 3-wire SPI mode SPISTE inversion for digital audio interface receive mode on devices with 2 SPI modules (This feature is not available on TMS320x2802x devices).

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1.1

SPI Block Diagram
Figure 2 is a block diagram of the SPI in slave mode, showing the basic control blocks available on the SPI module. Figure 2. Serial Peripheral Interface Module Block Diagram
SPIFFENA SPIFFTX.14 RX FIFO Registers SPIRXBUF RX FIFO _0 RX FIFO _1 ----RX FIFO _3 16 SPIRXBUF Buffer Register SPIFFOVF FLAG SPIFFRX.15 TX FIFO Registers SPITXBUF TX FIFO _3 ----TX FIFO _1 TX FIFO _0 16 16 SPITXBUF Buffer Register TX FIFO Interrupt To CPU

Receiver Overrun Flag SPISTS.7

Overrun INT ENA

SPICTL.4

RX FIFO Interrupt

SPIINT RX Interrupt Logic

TX Interrupt Logic SPITX

SPI INT FLAG SPISTS.6

SPI INT ENA

SPICTL.0 TRIWIRE 16 M SPIDAT Data Register M S S M SW1 M TW TW S S Talk SPICTL.1 STEINV SPISTE Master/Slave SPI Char SPICCR.3 - 0 3 2 1 0 M S S SPICTL.2 SW3 Clock Polarity SPICCR.6 1 0 M Clock Phase SPICTL.3 SPICLK SW2 SPISOMI STEINV SPIPRI.1 TW SPISIMO SPIPRI.0

SPIDAT.15 - 0

State Control

SPI Bit Rate LSPCLK 6 5 SPIBRR.6 - 0 4 3 2

A B

SPISTE of a slave device is driven low by the master. STEINV feature is not avaliable on TMS320x2802x devices.

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1.2

SPI Module Signal Summary
Table 1. SPI Module Signal Summary
Signal Name External Signals SPICLK SPISIMO/SPIMOMI (1) SPISOMI/SPISISO (1) SPISTE Control SPI Clock Rate Interrupt signals SPIRXINT SPITXINT
(1)

Description SPI clock SPI slave in, master out/ SPI master out, master in SPI slave out, master in/ SPI slave in, slave out SPI slave transmit enable LSPCLK Transmit interrupt/ Receive Interrupt in non FIFO mode (referred to as SPI INT) Receive in interrupt in FIFO mode Transmit interrupt – FIFO

In 3-wire master mode, the SPISIMO pin becomes the SPIMOMI pin and the SPISOMI pin becomes a general purpose input/output (GPIO) pin. In 3-wire slave mode, the SPISOMI pin becomes the SPISISO pin and the SPISIMO pin becomes a GPIO pin.

1.3

Overview of SPI Module Registers
The SPI port operation is configured and controlled by the registers listed in Table 2. Table 2. SPI Registers
Name SPICCR SPICTL SPIST SPIBRR SPIEMU SPIRXBUF SPITXBUF SPIDAT SPIFFTX SPIFFRX SPIFFCT SPIPRI Address Range 0x0000-7040 0x0000-7041 0x0000-7042 0x0000-7044 0x0000-7046 0x0000-7047 0x0000-7048 0x0000-7049 0x0000-704A 0x0000-704B 0x0000-704C 0x0000-704F Size (x16) 1 1 1 1 1 1 1 1 1 1 1 1 Description SPI Configuration Control Register SPI Operation Control Register SPI Status Register SPI Baud Rate Register SPI Emulation Buffer Register SPI Serial Input Buffer Register SPI Serial Output Buffer Register SPI Serial Data Register SPI FIFO Transmit Register SPI FIFO Receive Register SPI FIFO Control Register SPI Priority Control Register

This SPI has 16-bit transmit and receive capability, with double-buffered transmit and double-buffered receive. All data registers are 16-bits wide. The SPI is no longer limited to a maximum transmission rate of LSPCLK/8 in slave mode. The maximum transmission rate in both slave mode and master mode is now LSPCLK/4. Writes of transmit data to the serial data register, SPIDAT (and the new transmit buffer, SPITXBUF), must be left-justified within a 16-bit register. The control and data bits for general-purpose bit I/O multiplexing have been removed from this peripheral, along with the associated registers, SPIPC1 (704Dh) and SPIPC2 (704Eh). These bits are now in the General-Purpose I/O registers. Twelve registers inside the SPI module control the SPI operations: SPICCR (SPI configuration control register). Contains control bits used for SPI configuration – SPI module software reset – SPICLK polarity selection
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– Four SPI character-length control bits SPICTL (SPI operation control register). Contains control bits for data transmission – Two SPI interrupt enable bits – SPICLK phase selection – Operational mode (master/slave) – Data transmission enable SPISTS (SPI status register). Contains two receive buffer status bits and one transmit buffer status bit – RECEIVER OVERRUN – SPI INT FLAG – TX BUF FULL FLAG SPIBRR (SPI baud rate register). Contains seven bits that determine the bit transfer rate SPIRXEMU (SPI receive emulation buffer register). Contains the received data. This register is used for emulation purposes only. The SPIRXBUF should be used for normal operation SPIRXBUF (SPI receive buffer — the serial receive buffer register). Contains the received data SPITXBUF (SPI transmit buffer — the serial transmit buffer register). Contains the next character to be transmitted SPIDAT (SPI data register). Contains data to be transmitted by the SPI, acting as the transmit/receive shift register. Data written to SPIDAT is shifted out on subsequent SPICLK cycles. For every bit shifted out of the SPI, a bit from the receive bit stream is shifted into the other end of the shift register SPIPRI (SPI priority register). Contains bits that specify interrupt priority and determine SPI operation on the XDS emulator during program suspensions. This register also contains bit to enable 3-wire mode and the SPISTE inversion bit.

1.4

SPI Operation
This section describes the operation of the SPI. Included are explanations of the operation modes, interrupts, data format, clock sources, and initialization. Typical timing diagrams for data transfers are given.

1.4.1

Introduction to Operation Figure 3 shows typical connections of the SPI for communications between two controllers: a master and a slave. The master initiates data transfer by sending the SPICLK signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition (see Section 1.4.2). As a result, both controllers send and receive data simultaneously. The application software determines whether the data is meaningful or dummy data. There are three possible methods for data transmission: Master sends data; slave sends dummy data. Master sends data; slave sends data. Master sends dummy data; slave sends data. The master can initiate data transfer at any time because it controls the SPICLK signal. The software, however, determines how the master detects when the slave is ready to broadcast data.

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Figure 3. SPI Master/Slave Connection
SPI master (master/slave = 1) SPIRXBUF.150 Serial input buffer SPIRXBUF SPISTE SPIDAT.150
MSB

Slave in/ SPISIMO master out

SPI slave (master/slave = 0) SPISIMO SPIRXBUF.150 Serial input buffer SPIRXBUF

SPI strobe

SPISTE

Shift register LSB (SPIDAT)

SPISOMI

SPIDAT.150 Slave out/ SPISOMI Shift register MSB (SPIDAT) master in Serial clock

LSB

SPICLK SPITXBUF.150 Serial transmit buffer SPITXBUF Processor 1

SPICLK SPITXBUF.150 Serial transmit buffer SPITXBUF Processor 2

1.4.2

SPI Module Slave and Master Operation Modes The SPI can operate in master or slave mode. The MASTER/SLAVE bit (SPICTL.2) selects the operating mode and the source of the SPICLK signal.

1.4.2.1

Master Mode

In the master mode (MASTER/SLAVE = 1), the SPI provides the serial clock on the SPICLK pin for the entire serial communications network. Data is output on the SPISIMO pin and latched from the SPISOMI pin. The SPIBRR register determines both the transmit and receive bit transfer rate for the network. SPIBRR can select 126 different data transfer rates. Data written to SPIDAT or SPITXBUF initiates data transmission on the SPISIMO pin, MSB (most significant bit) first. Simultaneously, received data is shifted through the SPISOMI pin into the LSB (least significant bit) of SPIDAT. When the selected number of bits has been transmitted, the received data is transferred to the SPIRXBUF (buffered receiver) for the CPU to read. Data is stored right-justified in SPIRXBUF. When the specified number of data bits has been shifted through SPIDAT, the following events occur: SPIDAT contents are transferred to SPIRXBUF. SPI INT FLAG bit (SPISTS.6) is set to 1. If there is valid data in the transmit buffer SPITXBUF, as indicated by the TXBUF FULL bit in SPISTS, this data is transferred to SPIDAT and is transmitted; otherwise, SPICLK stops after all bits have been shifted out of SPIDAT. If the SPI INT ENA bit (SPICTL.0) is set to 1, an interrupt is asserted. In a typical application, the SPISTE pin serves as a chip-enable pin for a slave SPI device. This pin is driven low by the master before transmitting data to the slave and is taken high after the transmission is complete. 1.4.2.2 Slave Mode

In the slave mode (MASTER/SLAVE = 0), data shifts out on the SPISOMI pin and in on the SPISIMO pin. The SPICLK pin is used as the input for the serial shift clock, which is supplied from the external network master. The transfer rate is defined by this clock. The SPICLK input frequency should be no greater than the LSPCLK frequency divided by 4.
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Data written to SPIDAT or SPITXBUF is transmitted to the network when appropriate edges of the SPICLK signal are received from the network master. Data written to the SPITXBUF register will be transferred to the SPIDAT register when all bits of the character to be transmitted have been shifted out of SPIDAT. If no character is currently being transmitted when SPITXBUF is written to, the data will be transferred immediately to SPIDAT. To receive data, the SPI waits for the network master to send the SPICLK signal and then shifts the data on the SPISIMO pin into SPIDAT. If data is to be transmitted by the slave simultaneously, and SPITXBUF has not been previously loaded, the data must be written to SPITXBUF or SPIDAT before the beginning of the SPICLK signal. When the TALK bit (SPICTL.1) is cleared, data transmission is disabled, and the output line (SPISOMI) is put into the high-impedance state. If this occurs while a transmission is active, the current character is completely transmitted even though SPISOMI is forced into the high-impedance state. This ensures that the SPI is still able to receive incoming data correctly. This TALK bit allows many slave devices to be tied together on the network, but only one slave at a time is allowed to drive the SPISOMI line. The SPISTE pin operates as the slave-select pin. An active-low signal on the SPISTE pin allows the slave SPI to transfer data to the serial data line; an inactive- high signal causes the slave SPI serial shift register to stop and its serial output pin to be put into the high-impedance state. This allows many slave devices to be tied together on the network, although only one slave device is selected at a time.

1.5

SPI Interrupts
This section includes information on the control bits that initialize interrupts, data format, clocking, initialization, and data transfer.

1.5.1

SPI Interrupt Control Bits Five control bits are used to initialize the SPI interrupts: SPI INT ENA bit (SPICTL.0) SPI INT FLAG bit (SPISTS.6) OVERRUN INT ENA bit (SPICTL.4) RECEIVER OVERRUN FLAG bit (SPISTS.7)

1.5.1.1

SPI INT ENA Bit (SPICTL.0)

When the SPI interrupt-enable bit is set and an interrupt condition occurs, the corresponding interrupt is asserted. 0 1 Disable SPI interrupts Enable SPI interrupts

1.5.1.2

SPI INT FLAG Bit (SPISTS.6)

This status flag indicates that a character has been placed in the SPI receiver buffer and is ready to be read. When a complete character has been shifted into or out of SPIDAT, the SPI INT FLAG bit (SPISTS.6) is set, and an interrupt is generated if enabled by the SPI INT ENA bit (SPICTL.0). The interrupt flag remains set until it is cleared by one of the following events: The interrupt is acknowledged (this is different from the C240). The CPU reads the SPIRXBUF (reading the SPIRXEMU does not clear the SPI INT FLAG bit). The device enters IDLE2 or HALT mode with an IDLE instruction. Software clears the SPI SW RESET bit (SPICCR.7). A system reset occurs. When the SPI INT FLAG bit is set, a character has been placed into the SPIRXBUF and is ready to be read. If the CPU does not read the character by the time the next complete character has been received, the new character is written into SPIRXBUF, and the RECEIVER OVERRUN Flag bit (SPISTS.7) is set.
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1.5.1.3

OVERRUN INT ENA Bit (SPICTL.4)

Setting the overrun interrupt enable bit allows the assertion of an interrupt whenever the RECEIVER OVERRUN Flag bit (SPISTS.7) is set by hardware. Interrupts generated by SPISTS.7 and by the SPI INT FLAG bit (SPISTS.6) share the same interrupt vector. 0 1 Disable RECEIVER OVERRUN Flag bit interrupts Enable RECEIVER OVERRUN Flag bit interrupts

1.5.1.4

RECEIVER OVERRUN FLAG Bit (SPISTS.7)

The RECEIVER OVERRUN Flag bit is set whenever a new character is received and loaded into the SPIRXBUF before the previously received character has been read from the SPIRXBUF. The RECEIVER OVERRUN Flag bit must be cleared by software. 1.5.2 Data Format Four bits (SPICCR.3–0) specify the number of bits (1 to 16) in the data character. This information directs the state control logic to count the number of bits received or transmitted to determine when a complete character has been processed. The following statements apply to characters with fewer than 16 bits: Data must be left-justified when written to SPIDAT and SPITXBUF. Data read back from SPIRXBUF is right-justified. SPIRXBUF contains the most recently received character, right-justified, plus any bits that remain from previous transmission(s) that have been shifted to the left (shown in Example 1). Example 1. Transmission of Bit From SPIRXBUF Conditions: 1. Transmission character length = 1 bit (specified in bits SPICCR.30) 2. The current value of SPIDAT = 737Bh
SPIDAT (before transmission) 0 1 1 0 1 1 SPIDAT (after transmission) 1 1 0 1 1 1 SPIRXBUF (after transmission) 1 1 0 1 1 1

0 (TXed) 0 ← 1 1
(1)

1 1 1

1 1 1

1 0 0

0 0 0

1 1 1

1 0 0

0 1 1

1 1 1

1 x (1) x (1) ← (RXed)

x = 1 if SPISOMI data is high; x = 0 if SPISOMI data is low; master mode is assumed.

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1.5.3

Baud Rate and Clocking Schemes The SPI module supports 125 different baud rates and four different clock schemes. Depending on whether the SPI clock is in slave or master mode, the SPICLK pin can receive an external SPI clock signal or provide the SPI clock signal, respectively. In the slave mode, the SPI clock is received on the SPICLK pin from the external source, and can be no greater than the LSPCLK frequency divided by 4. In the master mode, the SPI clock is generated by the SPI and is output on the SPICLK pin, and can be no greater than the LSPCLK frequency divided by 4. Example 2 shows how to determine the SPI baud rates.

Example 2. Baud Rate Determination For SPIBRR = 3 to 127: LSPCLK SPI Baud Rate = (SPIBRR + 1) For SPIBRR = 0, 1, or 2: SPI Baud Rate = LSPCLK 4 where: LSPCLK = Low-speed peripheral clock frequency of the device SPIBRR = Contents of the SPIBRR in the master SPI device To determine what value to load into SPIBRR, you must know the device system clock (LSPCLK) frequency (which is device-specific) and the baud rate at which you will be operating. Example 12 shows how to determine the maximum baud rate at which a 240xA can communicate. Assume that LSPCLK = 40 MHz.

(1)

(2)

Example 3. Maximum Baud-Rate Calculation Maximum SPI Baud Rate = LSPCLK 4 40 × 10 6 = 4 = 10 × 10 6 bps

(3)

1.5.3.1

SPI Clocking Schemes

The CLOCK POLARITY bit (SPICCR.6) and the CLOCK PHASE bit (SPICTL.3) control four different clocking schemes on the SPICLK pin. The CLOCK POLARITY bit selects the active edge, either rising or falling, of the clock. The CLOCK PHASE bit selects a half-cycle delay of the clock. The four different clocking schemes are as follows: Falling Edge Without Delay. The SPI transmits data on the falling edge of the SPICLK and receives data on the rising edge of the SPICLK. Falling Edge With Delay. The SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. Rising Edge Without Delay. The SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. Rising Edge With Delay. The SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
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The selection procedure for the SPI clocking scheme is shown in Table 3. Examples of these four clocking schemes relative to transmitted and received data are shown in Figure 4. Table 3. SPI Clocking Scheme Selection Guide
SPICLK Scheme Rising edge without delay Rising edge with delay Falling edge without delay Falling edge with delay CLOCK POLARITY (SPICCR.6) 0 0 1 1 CLOCK PHASE (SPICTL.3) 0 1 0 1

Figure 4. SPICLK Signal Options
SPICLK cycle number SPICLK (Rising edge without delay) SPICLK (Rising edge with delay) SPICLK (Falling edge without delay) SPICLK (Falling edge with delay) SPISIMO/ SPISOMI SPISTE (Into slave) Receive latch points Note: Previous data bit
See note

1

2

3

4

5

6

7

8

MSB

LSB

For the SPI, SPICLK symmetry is retained only when the result of (SPIBRR+1) is an even value. When (SPIBRR + 1) is an odd value and SPIBRR is greater than 3, SPICLK becomes asymmetrical. The low pulse of SPICLK is one CLKOUT longer than the high pulse when the CLOCK POLARITY bit is clear (0). When the CLOCK POLARITY bit is set to 1, the high pulse of the SPICLK is one CLKOUT longer than the low pulse, as shown in Figure 5. Figure 5. SPI: SPICLK-CLKOUT Characteristic When (BRR + 1) is Odd, BRR > 3, and CLOCK POLARITY = 1
2 cycles CLKOUT 3 cycles 2 cycles

SPICLK

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1.5.4 A

Initialization Upon Reset system reset forces the SPI peripheral module into the following default configuration: Unit is configured as a slave module (MASTER/SLAVE = 0) Transmit capability is disabled (TALK = 0) Data is latched at the input on the falling edge of the SPICLK signal Character length is assumed to be one bit SPI interrupts are disabled Data in SPIDAT is reset to 0000h SPI module pin functions are selected as general-purpose inputs (this is done in I/O MUX control register B [MCRB]) this SPI configuration: Clear the SPI SW RESET bit (SPICCR.7) to 0 to force the SPI to the reset state. Initialize the SPI configuration, format, baud rate, and pin functions as desired. Set the SPI SW RESET bit to 1 to release the SPI from the reset state. Write to SPIDAT or SPITXBUF (this initiates the communication process in the master). Read SPIRXBUF after the data transmission has completed (SPISTS.6 = 1) to determine what data was received.

To change Step 1. Step 2. Step 3. Step 4. Step 5.

To prevent unwanted and unforeseen events from occurring during or as a result of initialization changes, clear the SPI SW RESET bit (SPICCR.7) before making initialization changes, and then set this bit after initialization is complete.
NOTE: Do not change the SPI configuration when communication is in progress.

1.5.5

Data Transfer Example The timing diagram shown in Figure 6 illustrates an SPI data transfer between two devices using a character length of five bits with the SPICLK being symmetrical. The timing diagram with SPICLK unsymmetrical (Figure 5) shares similar characterizations with Figure 6 except that the data transfer is one CLKOUT cycle longer per bit during the low pulse (CLOCK POLARITY = 0) or during the high pulse (CLOCK POLARITY = 1) of the SPICLK. Figure 6 is applicable for 8-bit SPI only and is not for 24x devices that are capable of working with 16-bit data. The figure is shown for illustrative purposes only.

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Figure 6. Five Bits per Character
Master SPI Int flag Slave SPI Int flag A B C SPISOMI from slave 7 SPISIMO from master SPICLK signal options: CLOCK POLARITY = 0 CLOCK PHASE = 0 7 6 5 4 3 7 6 5 4 3 6 5 4 3 7 6 5 4 3 D E F G H I J K

CLOCK POLARITY = 0 CLOCK PHASE = 1 CLOCK POLARITY = 1 CLOCK PHASE = 0 CLOCK POLARITY = 1 CLOCK PHASE = 1

SPISTE A B C D E F G H I J K Slave writes 0D0h to SPIDAT and waits for the master to shift out the data. Master sets the slave SPISTE signal low (active). Master writes 058h to SPIDAT, which starts the transmission procedure. First byte is finished and sets the interrupt flags. Slave reads 0Bh from its SPIRXBUF (right-justified). Slave writes 04Ch to SPIDAT and waits for the master to shift out the data. Master writes 06Ch to SPIDAT, which starts the transmission procedure. Master reads 01Ah from the SPIRXBUF (rightjustified). Second byte is finished and sets the interrupt flags. Master reads 89h and the slave reads 8Dh from their respective SPIRXBUF. After the user’s software masks off the unused bits, the master receives 09h and the slave receives 0Dh. Master clears the slave SPISTE signal high (inactive).

1.6

SPI FIFO Description
The following steps explain the FIFO features and help with programming the SPI FIFOs: 1. Reset. At reset the SPI powers up in standard SPI mode, the FIFO function is disabled. The FIFO registers SPIFFTX, SPIFFRX and SPIFFCT remain inactive. 2. Standard SPI. The standard 240x SPI mode will work with SPIINT/SPIRXINT as the interrupt source. 3. Mode change. FIFO mode is enabled by setting the SPIFFEN bit to 1 in the SPIFFTX register. SPIRST can reset the FIFO mode at any stage of its operation. 4. Active registers. All the SPI registers and SPI FIFO registers SPIFFTX, SPIFFRX, and SPIFFCT will be active. 5. Interrupts. FIFO mode has two interrupts one for transmit FIFO, SPITXINT and one for receive FIFO, SPIINT/SPIRXINT. SPIINT/SPIRXINT is the common interrupt for SPI FIFO receive, receive error and receive FIFO overflow conditions. The single SPIINT for both transmit and receive sections of the standard SPI will be disabled and this interrupt will service as SPI receive FIFO interrupt.

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6. Buffers. Transmit and receive buffers are supplemented with two FIFOs. The one-word transmit buffer (TXBUF) of the standard SPI functions as a transition buffer between the transmit FIFO and shift register. The one-word transmit buffer will be loaded from transmit FIFO only after the last bit of the shift register is shifted out. 7. Delayed transfer. The rate at which transmit words in the FIFO are transferred to transmit shift register is programmable. The SPIFFCT register bits (70) FFTXDLY7FFTXDLY0 define the delay between the word transfer. The delay is defined in number SPI serial clock cycles. The 8-bit register could define a minimum delay of 0 serial clock cycles and a maximum of 255 serial clock cycles. With zero delay, the SPI module can transmit data in continuous mode with the FIFO words shifting out back to back. With the 255 clock delay, the SPI module can transmit data in a maximum delayed mode with the FIFO words shifting out with a delay of 255 SPI clocks between each words. The programmable delay facilitates glueless interface to various slow SPI peripherals, such as EEPROMs, ADC, DAC etc. 8. FIFO status bits. Both transmit and receive FIFOs have status bits TXFFST or RXFFST (bits 12 0) that define the number of words available in the FIFOs at any time. The transmit FIFO reset bit TXFIFO and receive reset bit RXFIFO will reset the FIFO pointers to zero when these bits are set to 1. The FIFOs will resume operation from start once these bits are cleared to zero. 9. Programmable interrupt levels. Both transmit and receive FIFO can generate CPU interrupts. The interrupt trigger is generated whenever the transmit FIFO status bits TXFFST (bits 128) match (less than or equal to) the interrupt trigger level bits TXFFIL (bits 40 ). This provides a programmable interrupt trigger for transmit and receive sections of the SPI. The default value for these trigger level bits will be 0x11111 for receive FIFO and 0x00000 for transmit FIFO respectively. 1.6.1 SPI Interrupts Figure 7. SPI FIFO Interrupt Flags and Enable Logic Generation
4 x 16-bit FIFO RX FIFO 3 . . . RX FIFO 0 SPIFFENA OVRNINTENA RX BUF SPI SOMI SPIDAT SPI SIMO TX BUF SPIINT flag SPIINTENA RX_OVRN flag 0 RXFFOVF flag RXFFIL RXFFIENA 1 SPIRXINT

TX FIFO 0 . . . TX FIFO 3 TXFFIL

TXFFIENA

SPIFFENA 0 SPITXINT 1

Table 4. SPI Interrupt Flag Modes
SPI Interrupt FIFO Options SPI without FIFO Receive overrun Data receive Transmit empty
(1)

Interrupt Flags RXOVRN SPIINT SPIINT

Interrupt Enables OVRNINTENA SPIINTENA SPIINTENA

FIFO Enable SPIFFENA 0 0 0

Interrupt line

(1)

Source

SPIRXINT SPIRXINT SPIRXINT

In non FIFO mode, SPIRXINT is the same as the SPIINT interrupt in 240x devices. SPRUG71B – February 2009 – Revised October 2009 Submit Documentation Feedback
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Table 4. SPI Interrupt Flag Modes (continued)
SPI Interrupt SPI FIFO mode FIFO receive Transmit empty RXFFIL TXFFIL RXFFIENA TXFFIENA 1 1 SPIRXINT SPITXINT Interrupt Interrupt FIFO Enable Interrupt
(1)

1.7

SPI 3-Wire Mode Description
SPI 3-wire mode allows for SPI communication over 3 pins instead of the normal 4 pins. In master mode, if the TRIWIRE (SPIPRI.0) bit is set, enabling 3-wire SPI mode, SPISIMOx becomes the bi-directional SPIMOMIx (SPI master out, master in) pin, and SPISOMIx is no longer used by the SPI. In slave mode, if the TRIWIRE bit is set, SPISOMIx becomes the bi-directional SPISISOx (SPI slave in, slave out) pin, and SPISIMOx is no longer used by the SPI. The table below indicates the pin function differences between 3-wire and 4-wire SPI mode for a master and slave SPI. Table 5. 4-wire vs. 3-wire SPI Pin Functions
4-wire SPI SPICLKx SPISTEx SPISIMOx SPISOMIx 3-wire SPI (Master) SPICLKx SPISTEx SPIMOMIx Free 3-wire SPI(Slave) SPICLKx SPISTEx Free SPISISOx

Because in 3-wire mode, the receive and transmit paths within the SPI are connected, any data transmitted by the SPI module is also received by itself. The application software must take care to perform a dummy read to clear the SPI data register of the additional received data. The TALK bit (SPICTL.1) plays an important role in 3-wire SPI mode. The bit must be set to transmit data and cleared prior to reading data. In master mode, in order to initiate a read, the application software must write dummy data to the SPI data register (SPIDAT or SPIRXBUF) while the TALK bit is cleared (no data is transmitted out the SPIMOMI pin) before reading from the data register.

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Figure 8. SPI 3-wire Master Mode
SPI Module Data RX SPIDAT Free pin GPIO MUX

Data TX Talk SPICTL.1 SPIMOMIx

Figure 9. SPI 3-wire Slave Mode
SPI Module Data RX SPIDAT SPISISOx GPIO MUX

Data TX Free pin Talk SPICTL.1

Table 6 indicates how data is received or transmitted in the various SPI modes while the TALK bit is set or cleared. Table 6. 3-Wire SPI Pin Configuration
Pin Mode 4-wire 3-pin mode SPIPRI[TRIWIRE] 0 1 SPICTL[TALK] Master Mode X 0 1 Slave Mode 4-wire 3-pin mode 0 1 X 0 1 RX Disconnect from SPI TX RX TX/RX TX RX TX/RX RX Disconnect from SPI SPISIMO SPISOMI

SPI 3-Wire Mode Code Examples In addition to the normal SPI initialization, to configure the SPI module for 3-wire mode, the TRIWIRE bit (SPIPRI.0) must be set to 1. After initialization, there are several considerations to take into account when transmitting and receiving data in 3-wire master and slave mode. The following examples demonstrate these considerations.

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In 3-wire master mode, SPICLKx, SPISTEx, and SPISIMOx pins must be configured as SPI pins (SPISOMIx pin can be configured as non-SPI pin). When the master transmits, it receives the data it transmits (because SPISIMOx and SPISOMIx are connected internally in 3-wire mode). Therefore, the junk data received must be cleared from the receive buffer every time data is transmitted. Example 4. 3-Wire Master Mode Transmit
Uint16 data; Uint16 dummy; SpiaRegs.SPICTL.bit.TALK = 1; // SpiaRegs.SPITXBUF = data; // Master transmits while(SpiaRegs.SPISTS.bit.INT_FLAG !=1) {} // dummy = SpiaRegs.SPIRXBUF; // // Enable Transmit path data Waits until data rx’d Clears junk data from itself bc it rx’d same data tx’d

To receive data in 3-wire master mode, the master must clear the TALK (SPICTL.1) bit to 0 to close the transmit path and then transmit dummy data in order to initiate the transfer from the slave. Because the TALK bit is 0, unlike in transmit mode, the master dummy data does not appear on the SPISIMOx pin, and the master does not receive its own dummy data. Instead, the data from the slave is received by the master. Example 5. 3-Wire Master Mode Receive
Uint16 rdata; Uint16 dummy; SpiaRegs.SPICTL.bit.TALK = 0; // Disable Transmit path SpiaRegs.SPITXBUF = dummy; // Send dummy to start tx // NOTE: because TALK = 0, data does not tx onto SPISIMOA pin while(SpiaRegs.SPISTS.bit.INT_FLAG !=1) {} // Wait until data received rdata = SpiaRegs.SPIRXBUF; // Master reads data

In 3-wire slave mode, SPICLKx, SPISTEx, and SPISOMIx pins must be configured as SPI pins (SPISIMOx pin can be configured as non-SPI pin). Like in master mode, when transmitting, the slave receives the data it transmits and must clear this junk data from its receive buffer. Example 6. 3-Wire Slave Mode Transmit
Uint16 data; Uint16 dummy; SpiaRegs.SPICTL.bit.TALK = 1; // SpiaRegs.SPITXBUF = data; // while(SpiaRegs.SPISTS.bit.INT_FLAG !=1) {} // dummy = SpiaRegs.SPIRXBUF; //

Enable Transmit path Slave transmits data Wait until data rx’d Clears junk data from itself

As in 3-wire master mode, the TALK bit must be cleared to 0. Otherwise, the slave receives data normally. Example 7. - 3-Wire Slave Mode Receive
Uint16 rdata; SpiaRegs.SPICTL.bit.TALK = 0; // Disable Transmit path while(SpiaRegs.SPISTS.bit.INT_FLAG !=1) {} // Waits until data rx’d rdata = SpiaRegs.SPIRXBUF; // Slave reads data

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1.8

SPI STEINV Bit in Digital Audio Transfers
On those 2803x devices with 2 SPI modules, enabling the STEINV bit (SPIPRI.1) on one of the SPI modules allows the pair of SPIs to receive both left and right-channel digital audio data in slave mode. The SPI module that receives a normal active-low SPISTE signal stores right-channel data, and the SPI module that receives an inverted active-high SPISTE signal stores left-channel data from the master. To receive digital audio data from a digital audio interface receiver, the SPI modules can be connected as shown in Figure 10. Figure 10. SPI Digital Audio Receiver Configuration Using 2 SPIs
SPICLKA SPISIMOA SPI-A SPISOMIA SPISTEA SPISOMIB SPISTEB SPICLKB SPISIMIB SPI-B

DIGITAL AUDIO RECEiVER

Standard 28x SPI timing requirements limit the number of digital audio interface formats supported using the 2-SPI configuration with the STEINV bit. See your device-specific data sheet electricals for SPI timing requirements. With the SPI clock phase configured such that the CLOCK POLARITY (SPICCR.6) bit is 0 and the CLOCK PHASE (SPICTL.3) bit is 1 (data latched on rising edge of clock), standard right-justified digital audio interface data format is supported as shown in Figure 11. Figure 11. Standard Right-Justified Digital Audio Data Format
1/fs

SPI-B Receive (SPISTE invert) L/R CLK AUDIO BIT CLK DATA OUT
0 n n-1 2 1 0

DATA OUT
SPI-A Receive (normal SPISTE) R-channel SPISTEA/B SPICLKA/B
n n-1 2 1 0

AUDIOBIT CLK
L-channel

L/R CLK

SPISIMOA/B

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SPI Registers and Waveforms

2

SPI Registers and Waveforms
This section contains the registers, bit descriptions, and waveforms.

2.1

SPI Control Registers
The SPI is controlled and accessed through registers in the control register file.

2.1.1

SPI Configuration Control Register (SPICCR) SPICCR controls the setup of the SPI for operation. Figure 12. SPI Configuration Control Register (SPICCR) — Address 7040h
7 6 CLOCK POLARITY R/W-0 5 Reserved R-0 4 SPILBK R-0 3 SPI CHAR3 R/W-0 2 SPI CHAR2 R/W-0 1 SPI CHAR1 R/W-0 0 SPI CHAR0 R/W-0

SPI SW Reset R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. SPI Configuration Control Register (SPICCR) Field Descriptions
Bit 7 Field SPI SW RESET 0 Value Description SPI software reset. When changing configuration, you should clear this bit before the changes and set this bit before resuming operation. Initializes the SPI operating flags to the reset condition. Specifically, the RECEIVER OVERRUN Flag bit (SPISTS.7), the SPI INT FLAG bit (SPISTS.6), and the TXBUF FULL Flag bit (SPISTS.5) are cleared. The SPI configuration remains unchanged. If the module is operating as a master, the SPICLK signal output returns to its inactive level. SPI is ready to transmit or receive the next character. When the SPI SW RESET bit is a 0, a character written to the transmitter will not be shifted out when this bit is set. A new character must be written to the serial data register. Shift Clock Polarity. This bit controls the polarity of the SPICLK signal. CLOCK POLARITY and CLOCK PHASE (SPICTL.3) control four clocking schemes on the SPICLK pin. See Section 1.5.3. 0 Data is output on rising edge and input on falling edge. When no SPI data is sent, SPICLK is at low level. The data input and output edges depend on the value of the CLOCK PHASE bit (SPICTL.3) as follows: CLOCK PHASE = 0: Data is output on the rising edge of the SPICLK signal; input data is latched on the falling edge of the SPICLK signal. CLOCK PHASE = 1: Data is output one half-cycle before the first rising edge of the SPICLK signal and on subsequent falling edges of the SPICLK signal; input data is latched on the rising edge of the SPICLK signal. 1 Data is output on falling edge and input on rising edge. When no SPI data is sent, SPICLK is at high level. The data input and output edges depend on the value of the CLOCK PHASE bit (SPICTL.3) as follows: CLOCK PHASE = 0: Data is output on the falling edge of the SPICLK signal; input data is latched on the rising edge of the SPICLK signal. CLOCK PHASE = 1: Data is output one half-cycle before the first falling edge of the SPICLK signal and on subsequent rising edges of the SPICLK signal; input data is latched on the falling edge of the SPICLK signal. 5 4 Reserved SPILBK 0 1 3-0 SPI CHAR3 SPI CHAR0 Reads return zero; writes have no effect. SPI loopback. Loop back mode allows module validation during device testing. This mode is valid only in master mode of the SPI. SPI loop back mode disabled – default value after reset SPI loop back mode enabled, SIMO/SOMI lines are connected internally. Used for module self tests. Character Length Control Bits 3-0. These four bits determine the number of bits to be shifted in or out as a single character during one shift sequence. Table 8 lists the character length selected by the bit values.

1

6

CLOCK POLARITY

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Table 8. Character Length Control Bit Values
SPI CHAR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SPI CHAR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPI CHAR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPI CHAR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character Length 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

2.1.2

SPI Operation Control Register (SPICTL) SPICTL controls data transmission, the SPI’s ability to generate interrupts, the SPICLK phase, and the operational mode (slave or master). Figure 13. SPI Operation Control Register (SPICTL) — Address 7041h
7 6 Reserved R-0 5 4 OVERRUN INT ENA R/W-0 3 CLOCK PHASE R/W-0 2 MASTER/ SLAVE R/W-0 1 TALK R/W-0 0 SPI INT ENA R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. SPI Operation Control Register (SPICTL) Field Descriptions
Bit 7-5 4 Field Reserved Overrun INT ENA Value Description Reads return zero; writes have no effect. Overrun Interrupt Enable. Setting this bit causes an interrupt to be generated when the RECEIVER OVERRUN Flag bit (SPISTS.7) is set by hardware. Interrupts generated by the RECEIVER OVERRUN Flag bit and the SPI INT FLAG bit (SPISTS.6) share the same interrupt vector. 0 1 3 CLOCK PHASE Disable RECEIVER OVERRUN Flag bit (SPISTS.7) interrupts Enable RECEIVER OVERRUN Flag bit (SPISTS.7) interrupts SPI Clock Phase Select. This bit controls the phase of the SPICLK signal. CLOCK PHASE and CLOCK POLARITY (SPICCR.6) make four different clocking schemes possible (see Figure 4). When operating with CLOCK PHASE high, the SPI (master or slave) makes the first bit of data available after SPIDAT is written and before the first edge of the SPICLK signal, regardless of which SPI mode is being used. 0 1 2 MASTER / SLAVE 0 1 Normal SPI clocking scheme, depending on the CLOCK POLARITY bit (SPICCR.6) SPICLK signal delayed by one half-cycle; polarity determined by the CLOCK POLARITY bit SPI Network Mode Control. This bit determines whether the SPI is a network master or slave. During reset initialization, the SPI is automatically configured as a network slave. SPI configured as a slave. SPI configured as a master.

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Table 9. SPI Operation Control Register (SPICTL) Field Descriptions (continued)
Bit 1 Field TALK Value Description Master/Slave Transmit Enable. The TALK bit can disable data transmission (master or slave) by placing the serial data output in the high-impedance state. If this bit is disabled during a transmission, the transmit shift register continues to operate until the previous character is shifted out. When the TALK bit is disabled, the SPI is still able to receive characters and update the status flags. TALK is cleared (disabled) by a system reset. 0 Disables transmission: Slave mode operation: If not previously configured as a general-purpose I/O pin, the SPISOMI pin will be put in the high-impedance state. Master mode operation: If not previously configured as a general-purpose I/O pin, the SPISIMO pin will be put in the high-impedance state. 1 0 SPI INT ENA 0 1 Enables transmission For the 4-pin option, ensure to enable the receiver’s SPISTE input pin. SPI Interrupt Enable. This bit controls the SPI’s ability to generate a transmit/receive interrupt. The SPI INT FLAG bit (SPISTS.6) is unaffected by this bit. Disables interrupt Enables interrupt

2.1.3

SPI Status Register (SPIST) Figure 14. SPI Status Register (SPIST) — Address 7042h
7 6 SPI INT FLAG (1) (2) R/C-0 5 TX BUF FULL FLAG (2) R/C-0 4 Reserved 0

RECEIVER OVERRUN FLAG (1) (2) R/C-0
(1) (2)

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset The RECEIVER OVERRUN FLAG bit and the SPI INT FLAG bit share the same interrupt vector. Writing a 0 to bits 5, 6, and 7 has no effect.

Table 10. SPI Status Register (SPIST) Field Descriptions
Bit 7 Field RECEIVER OVERRUN FLAG Value Description SPI Receiver Overrun Flag. This bit is a read/clear-only flag. The SPI hardware sets this bit when a receive or transmit operation completes before the previous character has been read from the buffer. The bit indicates that the last received character has been overwritten and therefore lost (when the SPIRXBUF was overwritten by the SPI module before the previous character was read by the user application). The SPI requests one interrupt sequence each time this bit is set if the OVERRUN INT ENA bit (SPICTL.4) is set high. The bit is cleared in one of three ways: Writing a 1 to this bit Writing a 0 to SPI SW RESET (SPICCR.7) Resetting the system If the OVERRUN INT ENA bit (SPICTL.4) is set, the SPI requests only one interrupt upon the first occurrence of setting the RECEIVER OVERRUN Flag bit. Subsequent overruns will not request additional interrupts if this flag bit is already set. This means that in order to allow new overrun interrupt requests the user must clear this flag bit by writing a 1 to SPISTS.7 each time an overrun condition occurs. In other words, if the RECEIVER OVERRUN Flag bit is left set (not cleared) by the interrupt service routine, another overrun interrupt will not be immediately re-entered when the interrupt service routine is exited. 0 1 Writing a 0 has no effect Clears this bit. The RECEIVER OVERRUN Flag bit should be cleared during the interrupt service routine because the RECEIVER OVERRUN Flag bit and SPI INT FLAG bit (SPISTS.6) share the same interrupt vector. This will alleviate any possible doubt as to the source of the interrupt when the next byte is received.

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Table 10. SPI Status Register (SPIST) Field Descriptions (continued)
Bit 6 Field SPI INT FLAG Value Description SPI Interrupt Flag. SPI INT FLAG is a read-only flag. The SPI hardware sets this bit to indicate that it has completed sending or receiving the last bit and is ready to be serviced. The received character is placed in the receiver buffer at the same time this bit is set. This flag causes an interrupt to be requested if the SPI INT ENA bit (SPICTL.0) is set. 0 1 Writing a 0 has no effect This bit is cleared in one of three ways: Reading SPIRXBUF Writing a 0 to SPI SW RESET (SPICCR.7) Resetting the system 5 TX BUF FULL FLAG 0 1 4-0 Reserved 10 SPI Transmit Buffer Full Flag. This read-only bit gets set to 1 when a character is written to the SPI Transmit buffer SPITXBUF. It is cleared when the character is automatically loaded into SPIDAT when the shifting out of a previous character is complete. Writing a 0 has no effect This bit is cleared at reset. Reads return zero; writes have no effect.

2.1.4

SPI Baud Rate Register (SPIBRR) SPIBRR contains the bits used for baud-rate selection. Figure 15. SPI Baud Rate Register (SPIBRR) — Address 7044h
7 6
SPI BIT RATE 6

5
SPI BIT RATE 5

4
SPI BIT RATE 4

3
SPI BIT RATE 3

2
SPI BIT RATE 2

1
SPI BIT RATE 1

0
SPI BIT RATE 0

Reserved

R-0

RW-0

RW-0

RW-0

RW-0

RW-0

RW-0

RW-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. Field Descriptions
Bit 7 6-0 Field Reserved SPI BIT RATE 6 SPI BIT RATE 0 Value Description Reads return zero; writes have no effect. SPI Bit Rate (Baud) Control. These bits determine the bit transfer rate if the SPI is the network master. There are 125 data-transfer rates (each a function of the CPU clock, LSPCLK) that can be selected. One data bit is shifted per SPICLK cycle. (SPICLK is the baud rate clock output on the SPICLK pin.) If the SPI is a network slave, the module receives a clock on the SPICLK pin from the network master; therefore, these bits have no effect on the SPICLK signal. The frequency of the input clock from the master should not exceed the slave SPI’s SPICLK signal divided by 4. In master mode, the SPI clock is generated by the SPI and is output on the SPICLK pin. The SPI baud rates are determined by the following formula:

SPI Baud Rate =
For SPIBRR = 3 to 127: For SPIBRR = 0, 1, or 2:

LSPCLK (SPIBRR + 1)

SPI Baud Rate = LSPCLK 4

where: LSPCLK = Function of CPU clock frequency X low-speed peripheral clock of the device SPIBRR = Contents of the SPIBRR in the master SPI device

2.1.5

SPI Emulation Buffer Register (SPIRXEMU) SPIRXEMU contains the received data. Reading SPIRXEMU does not clear the SPI INT FLAG bit (SPISTS.6). This is not a real register but a dummy address from which the contents of SPIRXBUF can be read by the emulator without clearing the SPI INT FLAG.

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Figure 16. SPI Emulation Buffer Register (SPIRXEMU) — Address 7046h
15 ERXB15 R-0 7 ERXB7 R-0 14 ERXB14 R-0 6 ERXB6 R-0 13 ERXB13 R-0 5 ERXB5 R-0 12 ERXB12 R-0 4 ERXB4 R-0 11 ERXB11 R-0 3 ERXB3 R-0 10 ERXB10 R-0 2 ERXB2 R-0 9 ERXB9 R-0 1 ERXB1 R-0 8 ERXB8 R-0 0 ERXB0 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. SPI Emulation Buffer Register (SPIRXEMU) Field Descriptions
Bit 15 Field ERXB15 ERXB0 Value Description Emulation Buffer Received Data. SPIRXEMU functions almost identically to SPIRXBUF, except that reading SPIRXEMU does not clear the SPI INT FLAG bit (SPISTS.6). Once the SPIDAT has received the complete character, the character is transferred to SPIRXEMU and SPIRXBUF, where it can be read. At the same time, SPI INT FLAG is set. This mirror register was created to support emulation. Reading SPIRXBUF clears the SPI INT FLAG bit (SPISTS.6). In the normal operation of the emulator, the control registers are read to continually update the contents of these registers on the display screen. SPIRXEMU was created so that the emulator can read this register and properly update the contents on the display screen. Reading SPIRXEMU does not clear the SPI INT FLAG bit, but reading SPIRXBUF clears this flag. In other words, SPIRXEMU enables the emulator to emulate the true operation of the SPI more accurately. It is recommended that you view SPIRXEMU in the normal emulator run mode.

2.1.6

SPI Serial Receive Buffer Register (SPIRXBUF) SPIRXBUF contains the received data. Reading SPIRXBUF clears the SPI INT FLAG bit (SPISTS.6). Figure 17. SPI Serial Receive Buffer Register (SPIRXBUF) — Address 7047h
15 14 RXB14 R-0 6 RXB6 R-0 13 RXB13 R-0 5 RXB5 R-0 12 RXB12 R-0 4 RXB4 R-0 11 RXB11 R-0 3 RXB3 R-0 10 RXB10 R-0 2 RXB2 R-0 9 RXB9 R-0 1 RXB1 R-0 8 RXB8 R-0 0 RXB0 R-0

RXB15 R-0 7 RXB7 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. SPI Serial Receive Buffer Register (SPIRXBUF) Field Descriptions
Bit 15 Field RXB15 RXB0 Value Description Received Data. Once SPIDAT has received the complete character, the character is transferred to SPIRXBUF, where it can be read. At the same time, the SPI INT FLAG bit (SPISTS.6) is set. Since data is shifted into the SPI’s most significant bit first, it is stored right-justified in this register.

2.1.7

SPI Serial Transmit Buffer Register (SPITXBUF) SPITXBUF stores the next character to be transmitted. Writing to this register sets the TX BUF FULL Flag bit (SPISTS.5). When transmission of the current character is complete, the contents of this register are automatically loaded in SPIDAT and the TX BUF FULL Flag is cleared. If no transmission is currently active, data written to this register falls through into the SPIDAT register and the TX BUF FULL Flag is not set. In master mode, if no transmission is currently active, writing to this register initiates a transmission in the same manner that writing to SPIDAT does.

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Figure 18. SPI Serial Transmit Buffer Register (SPITXBUF) — Address 7048h
15 TXB15 R-0 7 TXB7 R-0 14 TXB14 R-0 6 TXB6 R-0 13 TXB13 R-0 5 TXB5 R-0 12 TXB12 R-0 4 TXB4 R-0 11 TXB11 R-0 3 TXB3 R-0 10 TXB10 R-0 2 TXB2 R-0 9 TXB9 R-0 1 TXB1 R-0 8 TXB8 R-0 0 TXB0 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. SPI Serial Transmit Buffer Register (SPITXBUF) Field Descriptions
Bit 15 Field TXB15 TXB0 Value Description Transmit Data Buffer. This is where the next character to be transmitted is stored. When the transmission of the current character has completed, if the TX BUF FULL Flag bit is set, the contents of this register is automatically transferred to SPIDAT, and the TX BUF FULL Flag is cleared. Writes to SPITXBUF must be left-justified.

2.1.8

SPI Serial Data Register (SPIDAT) SPIDAT is the transmit/receive shift register. Data written to SPIDAT is shifted out (MSB) on subsequent SPICLK cycles. For every bit (MSB) shifted out of the SPI, a bit is shifted into the LSB end of the shift register. Figure 19. SPI Serial Data Register (SPIDAT) — Address 7049h
15 14 SDAT14 R-0 6 SDAT6 R-0 13 SDAT13 R-0 5 SDAT5 R-0 12 SDAT12 R-0 4 SDAT4 R-0 11 SDAT11 R-0 3 SDAT3 R-0 10 SDAT10 R-0 2 SDAT2 R-0 9 SDAT9 R-0 1 SDAT1 R-0 8 SDAT8 R-0 0 SDAT0 R-0

SDAT15 R-0 7 SDAT7 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. SPI Serial Data Register (SPIDAT) Field Descriptions
Bit 15 Field SDAT15 SDAT0 Value Description Serial data. Writing to the SPIDAT performs two functions: It provides data to be output on the serial output pin if the TALK bit (SPICTL.1) is set. When the SPI is operating as a master, a data transfer is initiated. When initiating a transfer, see the CLOCK POLARITY bit (SPICCR.6) described in Section 2.1.1 and the CLOCK PHASE bit (SPICTL.3) described in Section 2.1.2, for the requirements. In master mode, writing dummy data to SPIDAT initiates a receiver sequence. Since the data is not hardware-justified for characters shorter than sixteen bits, transmit data must be written in left-justified form, and received data read in right-justified form.

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2.1.9

SPI FIFO Transmit, Receive, and Control Registers Figure 20. SPI FIFO Transmit (SPIFFTX) Register Address 704Ah
15 14 SPIFFENA R/W0 6 TXFFINT CLR W0 13 TXFIFO R/W-1 5 TXFFIENA R/W-0 12 TXFFST4 R0 4 TXFFIL4 R/W-0 11 TXFFST3 R0 3 TXFFIL3 R/W-0 10 TXFFST2 R0 2 TXFFIL2 R/W-0 9 TXFFST1 R0 1 TXFFIL1 R/W-0 8 TXFFST0 R0 0 TXFFIL0 R/W-0

SPIRST R/W-1 7 TXFFINT Flag R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. SPI FIFO Transmit (SPIFFTX) Register Field Descriptions
Bit 15 Field SPIRST 0 1 14 SPIFFENA 0 1 13 TXFIFO Reset 0 1 12-8 TXFFST40 00000 00001 00010 00011 00100 7 TXFFINT 0 1 6 TXFFINT CLR 0 1 5 TXFFIENA 0 1 4-0 TXFFIL40 00000 Value Description SPI reset Write 0 to reset the SPI transmit and receive channels. The SPI FIFO register configuration bits will be left as is. SPI FIFO can resume transmit or receive. No effect to the SPI registers bits. SPI FIFO enhancements enable SPI FIFO enhancements are disabled SPI FIFO enhancements are enabled Transmit FIFO reset Write 0 to reset the FIFO pointer to zero, and hold in reset. Re-enable Transmit FIFO operation Transmit FIFO status Transmit FIFO is empty. Transmit FIFO has 1 word. Transmit FIFO has 2 words. Transmit FIFO has 3 words. Transmit FIFO has 4 words, which is the maximum. TXFIFO interrupt TXFIFO interrupt has not occurred, This is a read-only bit. TXFIFO interrupt has occurred, This is a read-only bit. TXFIFO clear Write 0 has no effect on TXFIFINT flag bit, Bit reads back a zero. Write 1 to clear TXFFINT flag in bit 7. TX FIFO interrupt enable TX FIFO interrupt based on TXFFIVL match (less than or equal to) will be disabled . TX FIFO interrupt based on TXFFIVL match (less than or equal to) will be enabled. TXFFIL40 transmit FIFO interrupt level bits. Transmit FIFO will generate interrupt when the FIFO status bits (TXFFST40) and FIFO level bits (TXFFIL40 ) match (less than or equal to). Default value is 0x00000.

Figure 21. SPI FIFO Receive (SPIFFRX) Register Address 704Bh
15 R-0 7 RXFFINT Flag R-0 14 W0 6 RXFFINT CLR W0 13 RXFIFO Reset R/W1 5 RXFFIENA R/W0 12 RXFFST4 R0 4 RXFFIL4 R/W1 11 RXFFST3 R0 3 RXFFIL3 R/W1 10 RXFFST2 R0 2 RXFFIL2 R/W1 9 RXFFST1 R0 1 RXFFIL1 R/W1 8 RXFFST0 R0 0 RXFFIL0 R/W1 RXFFOVF Flag RXFFOVF CLR

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Table 17. SPI FIFO Receive (SPIFFRX) Register Field Descriptions
Bit 15 Field RXFFOVF 0 1 14 RXFFOVF CLR 0 1 13 RXFIFO Reset 0 1 12-8 RXFFST40 00000 00001 00010 00011 00100 7 RXFFINT 0 1 6 RXFFINT CLR 0 1 5 RXFFIENA 0 1 4-0 RXFFIL40 11111 Value Description Receive FIFO overflow flag Receive FIFO has not overflowed. This is a read-only bit. Receive FIFO has overflowed, read-only bit. More than 16 words have been received in to the FIFO, and the first received word is lost. Receive FIFO overflow clear Write 0 does not affect RXFFOVF flag bit, Bit reads back a zero Write 1 to clear RXFFOVF flag in bit 15 Receive FIFO reset Write 0 to reset the FIFO pointer to zero, and hold in reset. Re-enable receive FIFO operation Receive FIFO Status Receive FIFO is empty. Receive FIFO has 1 word. Receive FIFO has 2 words. Receive FIFO has 3 words. Receive FIFO has 4 words. Receive FIFO has a maximum of 4 words. Receive FIFO interrupt RXFIFO interrupt has not occurred. This is a read-only bit. RXFIFO interrupt has occurred. This is a read-only bit. Receive FIFO interrupt clear Write 0 has no effect on RXFIFINT flag bit, Bit reads back a zero. Write 1 to clear RXFFINT flag in bit 7. RX FIFO interrupt enable RX FIFO interrupt based on RXFFIL match (greater than or equal to) will be disabled. RX FIFO interrupt based on RXFFIL match (greater than or equal to) will be enabled. Receive FIFO interrupt level bits Receive FIFO generates an interrupt when the FIFO status bits (RXFFST4–0) are greater than or equal to the FIFO level bits (RXFFIL4–0). The default value of these bits after reset is 11111. This avoids frequent interrupts after reset, as the receive FIFO will be empty most of the time.

Figure 22. SPI FIFO Control (SPIFFCT) Register Address 704Ch
15 Reserved R-0 7 FFTXDLY7 R/W-0 6 FFTXDLY6 R/W-0 5 FFTXDLY5 R/W-0 4 FFTXDLY4 R/W-0 3 FFTXDLY3 R/W-0 2 FFTXDLY2 R/W-0 1 FFTXDLY1 R/W-0 0 FFTXDLY0 R/W-0 8

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. SPI FIFO Control (SPIFFCT) Register Field Descriptions
Bit 15-8 Field Reserved Value Description

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Table 18. SPI FIFO Control (SPIFFCT) Register Field Descriptions (continued)
Bit 7-0 Field FFTXDLY70 0 Value Description FIFO transmit delay bits These bits define the delay between every transfer from FIFO transmit buffer to transmit shift register. The delay is defined in number SPI serial clock cycles. The 8-bit register could define a minimum delay of 0 serial clock cycles and a maximum of 255 serial clock cycles. In FIFO mode, the buffer (TXBUF) between the shift register and the FIFO should be filled only after the shift register has completed shifting of the last bit. This is required to pass on the delay between transfers to the data stream. In the FIFO mode TXBUF should not be treated as one additional level of buffer.

1

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2.1.10

SPI Priority Control Register (SPIPRI) Figure 23. SPI Priority Control Register (SPIPRI) — Address 704Fh
7 Reserved 6 5 SPI SUSP SOFT 4 SPI SUSP FREE 3 Reserved 2 1 STEINV 0 TRIWIRE

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. SPI Priority Control Register (SPIPRI) Field Descriptions
Bit 7-6 5-4 SPI SUSP SOFT SPI SUSP FREE Field Value Description Reads return zero; writes have no effect. These bits determine what occurs when an emulation suspend occurs (for example, when the debugger hits a breakpoint). The peripheral can continue whatever it is doing (free-run mode) or, if in stop mode, it can either stop immediately or stop when the current operation (the current receive/transmit sequence) is complete. 00 Transmission stops after midway in the bit stream while TSUSPEND is asserted. Once TSUSPEND is deasserted without a system reset, the remainder of the bits pending in the DATBUF are shifted. Example: If SPIDAT has shifted 3 out of 8 bits, the communication freezes right there. However, if TSUSPEND is later deasserted without resetting the SPI, SPI starts transmitting from where it had stopped (fourth bit in this case) and will transmit 8 bits from that point. The SCI module operates differently. If the emulation suspend occurs before the start of a transmission, (i.e., before the first SPICLK pulse) then the transmission will not occur. If the emulation suspend occurs after the start of a transmission, then the data will be shifted out to completion. When the start of transmission occurs is dependent on the baud rate used. Standard SPI mode: Stop after transmitting the words in the shift register and buffer. That is, after TXBUF and SPIDAT are empty. In FIFO mode: Stop after transmitting the words in the shift register and buffer. That is, after TX FIFO and SPIDAT are empty. x1 3-2 1 Reserved STEINV SPISTE inversion bit (Not available on TMS320x2802x devices). On devices with 2 SPI modules, inverting the SPISTE signal on one of the modules allows the device to receive left and right- channel digital audio data. 0 1 0 TRIWIRE 0 1 SPISTE is active low (normal) SPISTE is active high (inverted) SPI 3-wire mode enable Normal 4-wire SPI mode 3-wire SPI mode enabled. The unused pin becomes a GPIO pin. In master mode, the SPISIMO pin becomes the SPIMOMI (master receive and transmit) pin and SPISOMI is free for non-SPI use. In slave mode, the SIISOMI pin becomes the SPISISO (slave receive and transmit) pin and SPISIMO is free for non-SPI use. Free run, continue SPI operation regardless of suspend or when the suspend occurred.

10

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2.2

SPI Example Waveforms

Figure 24. CLOCK POLARITY = 0, CLOCK PHASE = 0 (All data transitions are during the rising edge, non-delayed clock. Inactive level is low.)

Ch1 Period 200 ns

SPICLK

SPISIMO

Figure 25. CLOCK POLARITY = 0, CLOCK PHASE = 1 (All data transitions are during the rising edge, but delayed by half clock cycle. Inactive level is low.)

Ch1 Period 200 ns

SPICLK

SPISIMO

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Figure 26. CLOCK POLARITY = 1, CLOCK PHASE = 0 (All data transitions are during the falling edge. Inactive level is high.)

Ch1 Period 199 ns

SPICLK

SPISIMO

Figure 27. CLOCK POLARITY = 1, CLOCK PHASE = 1 (All data transitions are during the falling edge, but delayed by half clock cycle. Inactive level is high.)

Ch1 Period 200 ns

SPICLK

SPISIMO

Figure 28. SPISTE Behavior in Master Mode (Master lowers SPISTE during the entire 16 bits of
36 Serial Peripheral Interface (SPI) SPRUG71B – February 2009 – Revised October 2009 Submit Documentation Feedback
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transmission.)

Ch1 Period 200 ns

SPICLK

SPISTE

Figure 29. SPISTE Behavior in Slave Mode (Slave’s SPISTE is lowered during the entire 16 bits of transmission.)

Ch1 Period 398 ns

SPISIMO

SPISTE

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Appendix A

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Appendix A Revision History
Technical changes made in this revision are shown in Table 20. Table 20. Changes in Revision A
Location Global Additions, Deletions, Modifications Reformatted the doc and cleared typos.

38

Revision History

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