IC datasheet pdf-HT46R23,pdf(8-Bit A_D Type OTP MCU)

HT46R23 8-Bit A/D Type OTP MCU
Features
· Operating voltage: · Up to 0.5ms instruction cycle with 8MHz system clock

fSYS=4MHz: 3.3V~5.5V fSYS=8MHz: 4.5V~5.5V
· 23 bidirectional I/O lines (max.) · 1 interrupt input shared with an I/O line · 16-bit programmable timer/event counter with overflow

at VDD=5V
· 8-level subroutine nesting · 8 channels 10-bit resolution (9-bit accuracy) A/D con-

verter
· 2-channel (6+2)/(7+1)-bit PWM output shared with

interrupt and 7-stage prescaler
· On-chip crystal and RC oscillator · Watchdog Timer · 4096?15 program memory PROM · 192?8 data memory RAM · Supports PFD for sound generation · HALT function and wake-up feature reduce power

two I/O lines
· Bit manipulation instruction · 15-bit table read instruction · 63 powerful instructions · All instructions in one or two machine cycles · Low voltage reset function · I2C BUS (slave mode) · 24/28-pin SKDIP/SOP package

consumption

General Description
The device is an 8-bit high performance RISC-like microcontroller designed for multiple I/O product applications. It is particularly suitable for use in products such as washing machine controllers and home appliances. A HALT feature is included to reduce power consumption. The program and option memories can be electrically programmed, making this microcontroller suitable for product development applications.

I C is a trademark of Philips Semiconductors.

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Block Diagram
P A 5 /IN T

In te rru p t C ir c u it S T A C K P ro g ra m R O M P ro g ra m C o u n te r IN T C

T M R T M R C P A 3 /P . D

M U

P r e s c a le r X P A 4 /T M R

fS

Y S

P A 4 S Y S C L K /4

In s tr u c tio n R e g is te r

M P

M U

X

D A T A M e m o ry P W

W D T P r e s c a le r M P O R T D

W D T

M U

X R C O S C M 1

P D C P D In s tr u c tio n D e c o d e r A L U T im in g G e n e ra to r S h ifte r P A 3 , P A 5 M U X

P D 0 /P W

M 0 ~ P D 1 /P W

8 -C h a n n e l A /D C o n v e rte r S T A T U S P B C P B P O R T B P B 0 /A N 0 ~ P B 7 /A N 7 P A 0 P A 3 P A 4 P A 5 P A 6 P A 7 ~ P /P /T /IN /S /S A 2 . D M R T D A C L

O S C 2

O S R E V D V S S

S D

C 1

A C C

L V R

O p tio n P R O M

P A C P A I2 C B U S S la v e M o d e P C P C C

P O R T A

P C 0 ~ P C 4

Pin Assignment
P B 5 /A N 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 P B 4 /A N 4 P B 5 /A N 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 P B 4 /A N 4 P A 3 /P . D P A 2 P A 1 P A 0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 V S S P C 0 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 P B 6 /A N 6 P B 7 /A N 7 P A 4 /T M R P A 5 /IN T P A 6 /S D A P A 7 /S C L O S C 2 O S C 1 V D D R E S P D 0 /P W M P C 1 P A 3 /P . D P A 2 P A 1 P A 0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 V S S P C 0 P C 1 P C 2 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 P B 6 /A N 6 P B 7 /A N 7 P A 4 /T M R P A 5 /IN T P A 6 /S D A P A 7 /S C L O S C 2 O S C 1 V D D R E S P D 1 /P W M 1 P D 0 /P W M 0 P C 4 P C 3

H T 4 6 R 2 3 2 4 S K D IP -A /S O P -A

H T 4 6 R 2 3 2 8 S K D IP -A /S O P -A

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Pin Description
Pin Name PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6/SDA PA7/SCL VSS PC0~PC4 I/O ROM Code Option Description

I/O

Pull-high

Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: port option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are disabled automatically.

I/O

Pull-high Wake-up PA3 or PFD I/O or Serial Bus ? Pull-high

Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by ROM code option. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). The PFD, TMR and INT are pin-shared with PA3, PA4 and PA5, respectively. Once the I2C BUS function is used, the internal registers related to PA6 and PA7 can not be used. Negative power supply, ground. Bidirectional 5-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: port option). Bidirectional 2-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: port option). The PWM0/PWM1 output function are pin-shared with PD0/PD1 (dependent on PWM optios). Schmitt trigger reset input. Active low. Positive power supply OSC1, OSC2 are connected to an RC network or a Crystal (determined by ROM code option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.

? I/O

PD0/PWM0 PD1/PWM1 RES VDD OSC1 OSC2

I/O

Pull-high I/O or PWM ? ? Crystal or RC

I ? I O

Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+5.5V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50°C to 125°C Operating Temperature...........................-40°C to 85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ?Absolute Maximum Ratings? may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

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D.C. Characteristics
Symbol VDD1 VDD2 IDD1 Parameter Operating Voltage Operating Voltage Operating Current (Crystal OSC) Test Conditions VDD ? ? Conditions fSYS=4MHz fSYS=8MHz Min. 3.3 4.5 ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0.7VDD 0.7VDD 0 0 0.9VDD 0.9VDD 2.7 4 10 -2 -5 40 10 ? Typ. ? ? 1.3 3.3 1.3 3.3 4 1 2 ? ? ? ? ? ? ? ? ? ? ? ? ? 3 8 20 -4 -10 60 30 ±0.5 Max. 5.5 5.5 3 5 3 5 8 2 4 5 10 1 2 VDD 0.3VDD 0.3VDD VDD VDD 0.4VDD 0.4VDD VDD VDD 3.3 ? ? ? ? 80 50 ±1 Ta=25°C Unit V V mA mA mA mA mA mA mA mA mA mA mA V V V V V V V V V V mA mA mA mA kW kW LSB

3.3V No load, f SYS=4MHz ADC disable 5V 3.3V No load, f SYS=4MHz ADC disable 5V 5V 3.3V No load, fsys=8MHz ADC disable No load 5V 3.3V

IDD2

Operating Current (RC OSC)

IDD3

Operating Current

IADC

Only ADC Enable, Others Disable

ISTB1

Standby Current (WDT Enabled) 5V 3.3V Standby Current (WDT Disabled) 5V A/D Input Voltage ?

No load, system HALT

ISTB2 VAD VIL1

No load, system HALT ? ? ? ? ? ? ? ? ? ?

Input Low Voltage for I/O Ports, 3.3V TMR and INT 5V Input High Voltage for I/O Ports, 3.3V TMR and INT 5V 3.3V Input Low Voltage (RES) 5V 3.3V Input High Voltage (RES) 5V Low Voltage Reset I/O Port Sink Current ?

VIH1

VIL2

VIH2 VLVR IOL

3.3V VOL=0.1VDD 5V VOL=0.1VDD

IOH

I/O Port Source Current

3.3V VOH=0.9VDD 5V VOH=0.9VDD ? ? ?

RPH EAD

3.3V Pull-high Resistance 5V A/D Conversion Error ?

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A.C. Characteristics
Symbol Parameter Test Conditions VDD 3.3V System Clock (Crystal OSC) 5V fSYS2 3.3V System Clock (RC OSC) 5V fTIMER tAD tADC tWDTOSC tRES tSST tINT tHBUS 3.3V Timer I/P Frequency (TMR) 5V A/D Clock Period A/D Conversion Time Watchdog Oscillator 5V External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width I2C BUS Clock Period ? ? ? ? 5V ? 3.3V Conditions ? ? ? ? ? ? ? ? ? ? ? Power-up, reset or wake-up from HALT ? Connect to external pull-high resistor 2kW Min. 400 400 400 400 0 0 1 ? 43 36 1 ? 1 64 Typ. ? ? ? ? ? ? ? 76 86 72 ? 1024 ? ? Max. 4000 8000 4000 8000 4000 8000 ? ? 168 144 ? ? ? ? Ta=25°C Unit kHz kHz kHz kHz kHz kHz ms tAD ms ms ms *tSYS ms *tSYS

fSYS1

Note: *tSYS=1/fSYS

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Functional Description
Execution flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program counter - PC The program counter (PC) controls the sequence in which the instructions stored in program PROM are executed and its contents specify full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.

S y s te m

C lo c k

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

O S C 2 ( R C o n ly ) P C P C P C + 1 P C + 2

. e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )

. e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )

. e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )

Execution flow

Mode Initial Reset External Interrupt Timer/Event Counter Overflow A/D Converter Interrupt I2C BUS Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine

Program Counter *11 0 0 0 0 0 *11 #11 S11 *10 0 0 0 0 0 *10 #10 S10 *9 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 PC+2 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 @2 @1 @0 #3 S3 #2 S2 #1 S1 #0 S0 *5 0 0 0 0 0 *4 0 0 0 0 1 *3 0 0 1 1 0 *2 0 1 0 1 0 *1 0 0 0 0 0 *0 0 0 0 0 0

Program counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits

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Program memory - PROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 4096?15 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
· Location 000H · Location 00CH

This area is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
· Location 010H

This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
· Location 004H

This area is reserved for the I2C BUS interrupt service program. If the I2C BUS interrupt resulting from a slave address is match or completed one byte of data transfer, and if the interrupt is enable and the stack is not full, the program begins execution at location 010H.
· Table location

This area is reserved for the external interrupt service program. If the INT input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
· Location 008H

This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
0 0 0 H 0 0 4 H 0 0 8 H 0 0 C H 0 1 0 H

D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e A /D C o n v e r te r In te r r u p t S u b r o u tin e H - B U S In te r r u p t S u b r o u tin e P ro g ra m M e m o ry

n 0 0 H n . . H

L o o k - u p T a b le ( 2 5 6 w o r d s )

. 0 0 H . . . H

L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to .

Any location in the PROM space can be used as look-up tables. The instructions ?TABRDC [m]? (the current page, 1 page=256 words) and ?TABRDL [m]? (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1 bit is read as ?0?. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements.

Program memory Table Location *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0

Instruction TABRDC [m] TABRDL [m]

Table location Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 1.40 7 February 8, 2002 P11~P8: Current program counter bits

HT46R23
Stack register - STACK This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a ?CALL? is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return addresses are stored). Data memory - RAM The data memory is designed with 224?8 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (192?8). Most are read/write, but some are read only. The special function registers include the indirect addressing registers (00H;02H), timer/event counter higher-order byte register (TMRH;0CH), timer/event counter low-order byte register (TMRL;0DH), timer/event counter control register (TMRC;0EH), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register (INTC0; 0BH), PWM data register (PWM0;1AH, PWM1;1BH), the I2C BUS slave address register (HADR;20H), the I2C BUS control register (HCR;21H), the I2C BUS status register (HSR;22H), the I2C BUS data register (HDR;23H), the A/D result lower-order byte register (ADRL;24H), the A/D result higher-order byte register (ADRH;25H), the A/D control register (ADCR;26H), the A/D clock setting register (ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H). The remaining space before the 40H is reserved for future expanded usage and reading these locations will get ?00H?. The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. Rev. 1.40 8
0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 . H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 . H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H H A D R H C R H S R H D R A D R L A D R H A D C R A C S R IN T C 1 P A P A C P B P B C P C P C C P D P D C P W M 0 P W M 1 : U n u s e d R e a d a s "0 0 " S T A T U S IN T C 0 T M R H T M R L T M R C S p e c ia l P u r p o s e D A T A M E M O R Y A C C P C L T B L P T B L H In d ir e c t A d d r e s s in g R e g is te r 0 M P 0 In d ir e c t A d d r e s s in g R e g is te r 1 M P 1

3 . H 4 0 H

. . H

G e n e ra l P u rp o s e D A T A M E M O R Y (1 9 2 B y te s )

RAM mapping

All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by ?SET [m].i? and ?CLR [m].i?. They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H).

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Indirect addressing register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] or [02H] will access data memory pointed to by MP0[01H] or MP1[03H] respectively. Reading location 00H or 02H itself indirectly will return the result 00H. Writing indirectly result in no operation. The memory pointer registers (MP0 and MP1 are 8-bit registers). Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ ....)

operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the ?CLR WDT? or ?HALT? instruction. The PD flag can be affected only by executing the ?HALT? or ?CLR WDT? instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt, an internal timer/event counter interrupt, the A/D converter interrupt and the I2C BUS interrupts. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of INTC0 and INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by Function

The ALU not only saves the results of a data operation but also changes the status register. Status register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PD flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PD flag. In addition Labels C Bits 0

C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared by system power-up or executing the ?CLR WDT? instruction. PD is set by executing the ?HALT? instruction. TO is cleared by system power-up or executing the ?CLR WDT? or ?HALT? instruction. TO is set by a WDT time-out. Unused bit, read as ?0? Status register

AC Z OV PD TO ?

1 2 3 4 5 6, 7

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a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit 4 of INTC0) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 5 of INTC0), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. The A/D converter interrupt is initialized by setting the A/D converter request flag (ADF; bit 6 of INTC0), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a subroutine call to location 0CH will occur. The related interrupt request flag (ADF) will be reset and the EMI bit cleared to disable further interrupts. Register Bit No. Label 0 Function stack is not full and the HIF bit is set, a subroutine call to location 10H will occur. The related interrupt request flag (HIF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ?RETI? instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, ?RET? or ?RETI? may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. a b c d Interrupt Source External Interrupt Timer/event Counter Overflow A/D Converter Interrupt I C BUS Interrupt
2

Priority Vector 1 2 3 4 04H 08H 0CH 10H

Controls the master (global) EMI interrupt (1= enabled; 0= disabled) EEI Controls the external interrupt (1= enabled; 0= disabled) Controls the timer/event counter interrupt (1= enabled; 0= disabled)

1

2

ETI

INTC0 (0BH)

3

Controls the A/D converter EADI interrupt (1= enabled; 0= disabled) EIF External interrupt request flag (1= active; 0= inactive) Internal timer/event counter request flag (1= active; 0= inactive) A/D converter request flag (1= active; 0= inactive) Unused bit, read as ?0?

The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), A/D converter request flag (ADF), the I2C BUS interrupt request flag (HIF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable A/D converter interrupt bit (EADI), enable I2C BUS interrupt bit (EHI) and enable master interrupt bit (EMI) constitute an interrupt control register 0 (INTC0) and an interrupt control register 1 (INTC1) which are located at 0BH and 1EH in the data memory. EMI, EEI, ETI, EADI, EHI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, EIF, ADF, HIF) are set, they will remain in the INTC0 and INTC1 register until the interrupts are serviced or cleared by a software instruction. Register Bit No. Label 0 1 2 INTC1 (1EH) 3 4 5 6 7 EHI ? ? ? HIF ? ? ? Function Controls the I2C BUS interrupt (1= enabled; 0= disabled) Unused bit, read as ?0? Unused bit, read as ?0? Unused bit, read as ?0? I2C BUS interrupt request flag (1= active; 0= inactive) Unused bit, read as ?0? Unused bit, read as ?0? Unused bit, read as ?0?

4

5

TF

6 7

ADF ?

INTC0 register The I C BUS interrupt is initialized by setting the I2C BUS interrupt request flag (HIF; bit 4 of INTC1), caused by a slave address match (HAAS=?1?) or one byte of data transfer is completed. When the interrupt is enabled, the
2

INTC1 register Rev. 1.40 10 February 8, 2002

HT46R23
It is recommended that a program does not use the ?CALL subroutine? within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the ?CALL? operates in the interrupt subroutine. Oscillator configuration There are two oscillator circuits in the microcontroller.
O S C 1 O S C 1

The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 72ms@5V. The WDT oscillator can be disabled by ROM code option to conserve power. Watchdog Timer - WDT The clock source of the WDT is implemented by an dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) decided by ROM code options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by a ROM code option. If the watchdog timer is disabled, all the executions related to the WDT result in no operation. Once an internal WDT oscillator (RC oscillator with period 72ms normally) is selected, it is divided by 212~215 (by ROM code option to get the WDT time-out period). The minimum period of WDT time-out period is about 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection the WDT ROM code option, longer time-out periods can be realized. If the WDT time-out is selected 215, the maximum time-out period is divided by 2 15 ~2 16 about 2.3s~4.7s. If the WDT oscillator is disabled, the WDT clock may still cone from the instruction clock and operate in the same manner except that in the halt state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize ?chip reset? and set the status bit TO. Whereas in the halt mode, the overflow will initialize a ?warm reset? only the PC and SP are reset to zero. To clear the contents of WDT, three methods are adopted; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two

O S C 2 C r y s ta l O s c illa to r

fS Y S /4 N M O S O p e n D r a in

O S C 2 R C O s c illa to r

System oscillator Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined by the ROM code option. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 30kW to 750kW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz).
S y s te m C lo c k /4 M a s k o p tio n s e le c t W D T O S C fs D iv id e r fs/2
8

W D T P r e s c a le r C K R T C K R T

M a s k O p tio n W D T C le a r

T im e - o fs /2 1 5 ~ fs /2 1 4 ~ fs /2 1 3 ~ fs /2 1 2 ~

u t R e s e t fs /2 1 6 fs /2 1 5 fs /2 1 4 fs /2 1 3

Watchdog Timer

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HT46R23
types of instruction, only one can be active depending on the ROM code option - ?CLR WDT times selection option?. If the ?CLR WDT? is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case ?CLR WDT1? and ?CLR WDT2? are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out. If the WDT time-out period is selected fs/212 (ROM code option), the WDT time-out period ranges from fs/212~fs/213, since the ?CLR WDT? or ?CLR WDT1? and ?CLR WDT2? instructions only clear the last two stages of the WDT. Power down operation - HALT The HALT mode is initialized by the ?HALT? instruction and results in the following...
· The system oscillator will be turned off but the WDT

the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur:
· RES reset during normal operation · RES reset during HALT · WDT time-out reset during normal operation

oscillator keeps running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain

The WDT time-out during HALT is different from other chip reset conditions, since it can perform a ?warm re set? that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the ?initial condition? when the reset conditions are met. By examining the PD and TO flags, the program can distinguish between different ?chip resets?.

unchanged.
· WDT will be cleared and recounted again (if the WDT

V D D R E S S S T T im e - o u t C h ip R e s e t tS
S T

clock is from the WDT oscillator).
· All of the I/O ports maintain their original status. · The PD flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a ?warm reset?. After the TO and PD flags are examined, the reason for chip reset can be determined. The PD flag is cleared by system power-up or executing the ?CLR WDT? instruction and is set when executing the ?HALT? instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP; the others keep their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by the ROM code option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to ?1? before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, Rev. 1.40 12

Reset timing chart
V
D D

R E S

Reset circuit

H A L T W D T
R E S

W a rm

R e s e t

O S C 1

S S T 1 0 - b it R ip p le C o u n te r S y s te m R e s e t

C o ld R e s e t

Reset configuration

February 8, 2002

HT46R23
TO 0 u 0 1 1 PD 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT WDT When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status are shown below. PC Interrupt 000H Disable Clear. After master reset, WDT begins counting

Note: ?u? means ?unchanged? To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state.

Timer/event Counter Off Input/output Ports SP Input mode Points to the top of the stack

The registers states are summarized in the following table. Register TMRL TMRH TMRC Program Counter MP0 MP1 ACC TBLP TBLH STATUS INTC0 INTC1 PA PAC PB PBC PC PCC PD PDC PWM0 PWM1 HADR HCR HSR HDR ADRL ADRH Rese t(Power On) xxxx xxxx xxxx xxxx 00-0 1000 000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx --00 xxxx -000 0000 ---0 ---0 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 ---- --11 ---- --11 xxxx xxxx xxxx xxxx xxxx xxx0--0 0--100- -0-1 xxxx xxxx xx-- ---xxxx xxxx WDT Time-out RES Reset (Normal Operation) (Normal Operation) xxxx xxxx xxxx xxxx 00-0 1000 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --1u uuuu -000 0000 ---0 ---0 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 ---- --11 ---- --11 xxxx xxxx xxxx xxxx xxxx xxx0--0 0--100- -0-1 xxxx xxxx xx-- ---xxxx xxxx xxxx xxxx xxxx xxxx 00-0 1000 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 ---0 ---0 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 ---- --11 ---- --11 xxxx xxxx xxxx xxxx xxxx xxx0--0 0--100- -0-1 xxxx xxxx xx-- ---xxxx xxxx RES Reset (HALT) xxxx xxxx xxxx xxxx 00-0 1000 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --01 uuuu -000 0000 ---0 ---0 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 ---- --11 ---- --11 xxxx xxxx xxxx xxxx xxxx xxx0--0 0--100- -0-1 xxxx xxxx xx-- ---xxxx xxxx WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uu-u uuuu 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --11 uuuu -uuu uuuu ---u ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu ---u uuuu ---- --uu ---- --uu uuuu uuuu uuuu uuuu uuuu uuuu--u u--uuu- -u-u uuuu uuuu uu-- ---uuuu uuuu

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HT46R23
Register ADCR ACSR Note: Rese t(Power On) 0100 0000 1--- --00 ?*? stands for ?warm reset? ?u? stands for ?unchanged? ?x? stands for ?unknown? WDT Time-out RES Reset (Normal Operation) (Normal Operation) 0100 0000 1--- --00 0100 0000 1--- --00 RES Reset (HALT) 0100 0000 1--- --00 WDT Time-out (HALT)* uuuu uuuu u--- --uu

Timer/Event Counter A timer/event counter (TMR) is implemented in the microcontroller. The timer/event counter contains an 16-bit programmable count-up counter and the clock may come from an external source or the system clock. Using the internal system clock, there is only one reference time-base. The internal clock source comes from fSYS. Using external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. There are three registers related to the timer/event counter; TMRH (0CH), TMRL (0DH), TMRC (0EH). Writing TMRL will only put the written data to an internal lower-order byte buffer (8 bits) and writing TMRH will transfer the specified data and the contents of the lower-order byte buffer to TMRH and TMRL preload registers, respectively. The timer/event counter preload register is changed by each writing TMRH operations. Reading TMRH will latch the contents of TMRH and TMRL counters to the destination and the lower-order byte buffer, respectively. Reading the TMRL will read the contents of the lower-order byte buffer. The TMRC is the timer/event counter control register, which defines the operating mode, counting enable or disable and active edge. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR) pin. The timer mode functions as a normal timer
P W M (6 + 2 ) o r (7 + 1 ) c o m p a re fS
Y S

with the clock source coming from the fINT clock. The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the fINT. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request flag (TF; bit 5 of INTC0) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bits is ?0?) it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by

T o P D 0 /P D 1 c ir c u it

8 - s ta g e p r e s c a le r 8 -1 M U X P S C 2 ~ P S C 0 T M R T E T M 1 T M 0 T O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r 1 /2 O v e r flo w to In te rru p t P . D f IN
T

D a ta B u s T M 1 T M 0 T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d

Timer/Event Counter

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HT46R23
instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt service. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMRH) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer. The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal. The timer prescaler is also used as the PWM counter. Label Bits (TMRC) Function all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, CMOS output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write ?1?. The input source also depends on the control register. If the control register bit is ?1?, the input will read the pad state. If the control register bit is ?0?, the contents of the latches will move to the internal bus. The latter is possible in the ?read-modify-write? instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 19H. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by ?SET [m].i? and ?CLR [m].i? (m=12H, 14H, 16H or 18H) instructions. Some instructions first input data and then follow the output operations. For example, ?SET [m].i?, ?CLR [m].i?, ?CPL [m]?, ?CPLA [m]? read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The highest 3-bit of port C and 6-bit of port D are not physically implemented; on reading them a ?0? is returned whereas writing then results in a no-operation. See Application note. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, there?s none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. The PA3 is pin-shared with the PFD signal. If the PFD option is selected, the output signal in output mode of PA3 will be the PFD signal generated by timer/event counter overflow signal. The input mode always remaining its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data register only. The I/O functions of PA3 are shown below. I/O I/P Mode (Normal) PA3 Note: Logical Input O/P (Normal) Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on)

To define the prescaler stages, PSC2, PSC1, PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 PSC0~ 0~2 011: fINT=fSYS/8 PSC2 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 To define the TMR active edge of timer/ event counter (0=active on low to high; 1=active on high to low) To enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as ?0? To define the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC register Input/output ports There are 23 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC and PD, which are mapped to the data memory of [12H], [14H], [16H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ?MOV A,[m]? (m=12H, 14H, 16H or 18H). For output operation,

TE

3

TON ?

4 5

TM0 TM1

6 7

The PFD frequency is the timer/event counter overflow frequency divided by 2.

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HT46R23
V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D C K Q S Q P U P A P A P A P A P A P B P C P D P D 0 ~ P A 2 3 /P . D 4 /T M R 5 /IN T 6 , P A 7 0 /A N 0 ~ P B 7 /A N 7 0 ~ P C 5 0 /P W M 0 1 /P W M 1
D D

D a ta B it Q D C K S Q M U X P . D E N (P A 3 ) U X O P 0 ~ O P 7

W r ite D a ta R e g is te r

(P D 0 o r P W M 0 ) P A 3 (P D 1 o r P W M 1 ) P . D M R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN T fo r P A 5 O n ly T M R fo r P A 4 O n ly

Input/output ports The PA5 and PA4 are pin-shared with INT and TMR pins respectively. The PB can also be used as A/D converter inputs. The A/D function will be described later. There is a PWM function shared with PD0/PD1. If the PWM function is enabled, the PWM0/PWM1 signal will appear on PD0/PD1 (if PD0/PD1 is operating in output mode). The I/O functions of PD0/PD1 are as shown. I/O I/P Mode (Normal) PD0 PD1 Logical Input O/P (Normal) Logical Output I/P (PWM) Logical Input O/P (PWM) PWM0 PWM1 A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is the value of PWM.1~PWM.0. In a (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~3) i<AC Modulation cycle i (i=0~3) i?AC PWM The microcontroller provides 2 channels (6+2)/(7+1) (dependent on options) bits PWM output shared with PD0/PD1. The PWM channels have their data registers denoted as PWM0 (1AH) and PWM1 (1BH). The frequency source of the PWM counter comes from fSYS. The PWM registers are two 8-bit registers. The waveforms of PWM outputs are as shown. Once the PD0/PD1 are selected as the PWM outputs and the output function of PD0/PD1 are enabled (PDC.0/PDC.1 =?0?), writing 1 to PD0/PD1 data register will enable the PWM output function and writing ?0? will force the PD0/PD1 to stay at ?0?. Duty Cycle DC + 1 64 DC 64

It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state.

A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle0~modulation cycle 1). Each modulation cycle has 128 PWM input clock period. In a (7+1) bits PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.1. The group 2 is denoted by AC which is the value of PWM.0.

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HT46R23
fS
Y S

/2

[P W M ] = 1 0 0 P W M [P W M ] = 1 0 1 P W M [P W M ] = 1 0 2 P W M [P W M ] = 1 0 3 P W M P W M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS
Y S

2 5 /6 4

2 5 /6 4

2 5 /6 4

2 5 /6 4

2 5 /6 4

2 6 /6 4

2 5 /6 4

2 5 /6 4

2 5 /6 4

2 6 /6 4

2 6 /6 4

2 6 /6 4

2 5 /6 4

2 5 /6 4

2 6 /6 4

2 6 /6 4 P W M

2 6 /6 4 c y c le : 2 5 6 /fS

2 5 /6 4

2 6 /6 4

Y S

(6+2) PWM mode

fS

Y S

/2

[P W M ] = 1 0 0 P W M [P W M ] = 1 0 1 P W M [P W M ] = 1 0 2 P W M [P W M ] = 1 0 3 P W M P W M 5 2 /1 2 8 m o d u la tio n p e r io d : 1 2 8 /fS
Y S

5 0 /1 2 8

5 0 /1 2 8

5 0 /1 2 8

5 1 /1 2 8

5 0 /1 2 8

5 1 /1 2 8

5 1 /1 2 8

5 1 /1 2 8

5 1 /1 2 8

5 1 /1 2 8 P W M c y c le : 2 5 6 /fS

5 2 /1 2 8

Y S

(7+1) PWM mode In a (7+1) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~1) i<AC Modulation cycle i (i=0~1) i?AC Duty Cycle DC + 1 128 DC 128 ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the users want to start an A/D conversion. Define PB configuration, select the converted analog channel, and give START bit a raising edge and falling edge (0?1?0). At the end of A/D conversion, the EOC bit is cleared and an A/D converter interrupt occurs (if the A/D converter interrupt is enabled). The ACSR is A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of eight channels to select. The bit5~bit3 of the ADCR are used to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D 17 February 8, 2002

The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency fSYS/64 for (6+2) bits mode fSYS/128 for (7+1) bits mode A/D converter The 8 channels and 10-bit resolution A/D (9-bit accuracy) converter are implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (24H), ADRH (25H), ADCR (26H) and ACSR (27H). The ADRH and Rev. 1.40 PWM Cycle PWM Cycle Frequency Duty fSYS/256 [PWM]/256

HT46R23
converter circuit is power on. The EOC bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure the A/D conversion is completed, the START should remain at ?0? until the EOC is cleared to ?0? (end of A/D conversion). The bit 7 of the ACSR is used for testing purposes only. It can not be used by the users. The bit1 and bit0 of the ACSR are used to select A/D clock sources. Label Bits (ACSR) Function Selects the A/D converter clock source 00= system clock?2 01= system clock?8 10= system clock?32 11= undefined ACS2 ACS1 ACS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Analog Channel A0 A1 A2 A3 A4 A5 A6 A7

Analog input channel selection When the A/D conversion is completed, the A/D interrupt request flag is set. The EOC bit is set to ?1? when the START bit is set from ?0? to ?1?. Register ADRL ADRH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 D1 D0 ? ? D6 ? D5 ? D4 ? D3 ? D2

ADCS0 ADCS1

0 1

? TEST

2~6 Unused bit, read as ?0? 7 For test mode used only ACSR register

D9 D8 D7

Note: *: D0~D9 is A/D conversion result data bit LSB~MSB.

Label Bits (ADCR) ACS0 ACS1 ACS2 PCR0 PCR1 PCR2 0 1 2 3 4 5

Function

Defines the analog channel select. Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is power off to reduce power consumption Provides response at the end of the A/D conversion. (0= end of A/D conversion) Starts the A/D conversion. (0?1?0 =start; 0?1? reset A/D converter) ADCR register

EOC

6

START

7

PCR2 0 0 0 0 1 1 1 1

PCR1 0 0 1 1 0 0 1 1

PCR0 0 1 0 1 0 1 0 1

7 PB7 PB7 PB7 PB7 PB7 PB7 PB7 A7

6 PB6 PB6 PB6 PB6 PB6 PB6 PB6 A6

5 PB5 PB5 PB5 PB5 PB5 PB5 A5 A5

4 PB4 PB4 PB4 PB4 PB4 A4 A4 A4

3 PB3 PB3 PB3 PB3 A3 A3 A3 A3

2 PB2 PB2 PB2 A2 A2 A2 A2 A2

1 PB1 PB1 A1 A1 A1 A1 A1 A1

0 PB0 A0 A0 A0 A0 A0 A0 A0

Port B configuration Rev. 1.40 18 February 8, 2002

HT46R23
S T A R T E O C *7 6 T A D P C R 0 ~ P C R 2 0 0 0 B 1 0 0 B *7 6 T A D 1 0 0 B 0 0 0 B

A C S 0 ~ A C S 2

0 0 0 B P o w e r O n R e s e t 1 : D 2 : S ***3 (E x fS Y N o te : e fin e le c : S e a m p S /8 ) e P t a le c le :

0 1 0 B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r r a tio n n n e l c k l, A N 2 ,

0 0 0 B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e rte r

**X X X B 1 : A ll P B lin e is d ig ita l in p u t 2 : A /D c o n v e r te r is p o w e r o ff to r e d u c e p o w e r c o n s u m p tio n E n d o f A /D c o n v e rte r

B c o n fig u n a lo g c h a t A D C c lo 4 c h a n n e

" * " A /D c o n v e r tin g tim e is 7 6 T A D " * * " X X X B m e a n s d o n 't c a r e " * * * " A D C c lo c k m u s t b e fS Y S /2 , fS

Y S

/8 , fS

Y S

/3 2

A/D conversion timing Low voltage reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~3.3V, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
· The low voltage (0.9V~3.3V) has to remain in their

The relationship between VDD and VLVR is shown below.
V D D 5 .5 V V
O P R

5 .5 V

V 3 .3 V 3 .0 V

L V R

original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function.
· The LVR uses the ?OR? function with the external RES

0 .9 V

signal to perform chip reset.
V 5 .5 V
D D

Note: VOPR is the voltage range for proper chip operation at 4MHz system clock.

V

L V R

L V R

D e te c t V o lta g e

0 .9 V 0 V R e s e t S ig n a l

R e s e t *1

N o r m a l O p e r a tio n *2

R e s e t

Low voltage reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.40 19 February 8, 2002

HT46R23
I2C BUS Serial Interface I C BUS is implemented in the device. The I C BUS is a bidirectional two-wire lines. The data line and clock line are implement in SDA pin and SCL pin. The SDA and SCL are NMOS open drain output pin. They must connect a pull-high resistor respectively. Using the I2C BUS, the device has two ways to transfer data. One is in slave transmit mode, the other is in slave receive mode. There are four registers related to I2C BUS; HADR([20H]), HCR([21H]), HSR([22H]), HDR([23H]). The HADR register is the slave address setting of the device, if the master sends the calling address which match, it means that this device is selected. The HCR is I2C BUS control register which defines the device enable or disable the I2C BUS as a transmitter or as a receiver. The HSR is I2C BUS status register, it responds with the I2C BUS status. The HDR is input/output data register, data to transmit or receive must be via the HDR register. The I2C BUS control register contains three bits. The HEN bit define the enable or disable the I2C BUS. If the data wants transfer via I2C BUS, this bit must be set. The HTX bit defines whether the I2C BUS is in transmit or receive mode. If the device is as a transmitter, this bit must be set to ?1?. The TXAK defines the transmit acknowledge signal, when the device received 8-bit data, the device sends this bit to I2C BUS at the 9th clock. If the receiver wants to continue to receive the next data, this bit must be reset to ?0? before receiving data. The I2C BUS status register contains 5 bits. The HCF bit is reset to ?0? when one data byte is being transferred. If one data transfer is completed, this bit is set to ?1?. The HASS bit is set ?1? when the address is match, and the I2C BUS interrupt request flag is set to ?1?. If the interrupt is enabled and the stack is not full, a subroutine call to location 10H will occur. Writing data to the I2C BUS control register clears HAAS bit. If the address is not match, this bit is reset to ?0?. The HBB bit is set to respond the I2C BUS is busy. It mean that a START signal is detected. This bit is reset to ?0? when the I2C BUS is not busy. It means that a STOP signal is detected and the I2C BUS is free. The SRW bit defines the read/write command bit, if the calling address is match. When HAAS is set to ?1?, the device check SRW bit to determine whether the device is working in transmit or receive mode. When SRW bit is set ?1?, it means that the master wants to read data from I2C BUS, the slave device must write data to I2C BUS, so the slave device is working in transmit mode. When SRW is reset to ?0?, it means that the master wants to write data to I2C BUS, the slave device must read data from the bus, so the slave device is working in receive mode. The RXAK bit is reset ?0? indicates an acknowledges signal has been received. In the transmit mode, the transmitter checks RXAK bit to know the receiver which wants to receive Rev. 1.40 20
2 2

the next data byte, so the transmitter continue to write data to the I2C BUS until the RXAK bit is set to ?1? and the transmitter releases the SDA line, so that the master can send the STOP signal to release the bus. The HADR bit7-bit1 define the device slave address. At the beginning of transfer, the master must select a device by sending the address of the slave device. The bit 0 is unused and is not defined. If the I2C BUS receives a start signal, all slave device notice the continuity of the 8-bit data. The front of 7 bits is slave address and the first bit is MSB. If the address is match, the HAAS status bit is set and generate an I2C BUS interrupt. In the ISR, the slave device must check the HAAS bit to know the I2C BUS interrupt comes from the slave address that has match or completed one 8-bit data transfer. The last bit of the 8-bit data is read/write command bit, it responds in SRW bit. The slave will check the SRW bit to know if the master wants to transmit or receive data. The device check SRW bit to know it is as a transmitter or receiver. Bit7~Bit1 Slave Address HADR register Note: ??? means undefined The HDR register is the I2C BUS input/output data register. Before transmitting data, the HDR must write the data which we want to transmit. Before receiving data, the device must dummy read data from HDR. Transmit or Receive data from I2C BUS must be via the HDR register. At the beginning of the transfer of the I2C BUS, the device must initial the bus, the following are the notes for initialing the I2C BUS: 1: Write the I2C BUS address register (HADR) to define its own slave address. 2: Set HEN bit of I2C BUS control register (HCR) bit 0 to enable the I2C BUS. Label Bits (HCR) HEN ? ? HTX TXAK ? 7 6 5 4 3 Function To enable/disable I2C BUS function (0= disable; 1= enable) Unused bit, read as ?0? Unused bit, read as ?0? To define the transmit/receive mode (0= receive mode; 1= transmit) To enable/disable transmit acknowledge (0= acknowledge; 1= don?t acknowledge) Bit0 ?

0~2 Unused bit, read as ?0? HCR register

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HT46R23
3: Set EHI bit of the interrupt control register 1 (INTC1) bit 0 to enable the I2C BUS interrupt. Label Bits (HSR) Function HCF is clear to ?0? when one data byte is being transferred, HCF is set to ?1? indicating 8-bit data communication has been finished. HAAS is set to ?1? when the calling addressed is matched, and I2C BUS interrupt will occur and HIF is set. HBB is set to ?1? when I2C BUS is busy and HBB is cleared to ?0? means that the I2C BUS is not busy. Unused bit, read as ?0? Unused bit, read as ?0? SRW is set to ?1? when the master wants to read data from the I2C BUS, so the slave must transmit data to the master. SRW is cleared to ?0? when the master wants to write data to the I2C BUS, so the slave must receive data from the master. Unused bit, read as ?0? RXAK is cleared to ?0? when the master receives an 8-bit data and acknowledgment at the 9th clock, RXAK is set to ?1? means not acknowledged. HSR register
S ta rt

Start signal The START signal is generated only by the master device. The other device in the bus must detect the START signal to set the I2C BUS busy bit (HBB). The START signal is SDA line from high to low, when SCL is high. Slave address The master must select a device for transferring the data by sending the slave device address after the START signal. All device in the I2C BUS will receive the I2C BUS slave address (7 bits) to compare with its own slave address (7 bits). If the slave address is matched, the slave device will generate an interrupt and save the following bit (8th bit) to SRW bit and sends an acknowledge bit (low level) to the 9th bit. The slave device also sets the status flag (HAAS), when the slave address is matched. In interrupt subroutine, check HAAS bit to know whether the I2C BUS interrupt comes from a slave address that is matched or a data byte transfer is completed. When the slave address is matched, the device must be in transmit mode or receive mode and write data to HDR or dummy read from HDR to release the SCL line. SRW bit The SRW bit means that the master device wants to read from or write to the I2C BUS. The slave device check this bit to understand itself if it is a transmitter or a receiver. The SRW bit is set to ?1? means that the master wants to read data from the I2C BUS, so the slave deS R W A C K

HCF

7

HAAS

6

HBB ? ?

5 4 3

SRW

2

?

1

RXAK

0

S C L

S D A

1

0

1

1

0

1

0

1

0

D a ta S C L

A C K

S to p

1 S D A

0

0

1

0

1

0

0

S = S A S R M = D = A = P = S

S ta = S = S S la D a A C S to

rt (1 la v e R W v e d ta (8 K (R p (1 S R

b it) A d d r b it ( 1 e v ic e b its ) X A K b it) M

e s s ( 7 b its ) b it) s e n d a c lc n o w le d g e b it ( 1 b it) b it fo r tr a n s m itte r ; T X A K b it fo r r e c e iv e r 1 b it)

S A

D

A

D

A

S

S A

S R

M

D

A

D

A

P

Slave address

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HT46R23
vice must write data to a bus as a transmitter. The SRW is cleared to ?0? means that the master wants to write data to the I2C BUS, so the slave device must read data from the I2C BUS as a receiver. Acknowledge bit One of the slave device generates an acknowledge signal, when the slave address is matched. The master device can check this acknowledge bit to know if the slave device accepts the calling address. If no acknowledge bit, the master must send a STOP bit and end the communication. When the I2C BUS status register bit 6 HAAS is high, it means the address is matched, so the slave must check SRW as a transmitter (set HTX) to ?1? or as a receiver (clear HTX) to ?0?. Data byte The data is 8 bits and is sent after the slave device has acknowledges the slave address. The first bit is MSB and the 8th bit is LSB. The receiver sends the acknowledge signal (?0?) and continues to receive the next one byte data. If the transmitter checks and there?s no acknowledge signal, then it release the SDA line, and the master sends a STOP signal to release the I2C BUS. The data is stored in the HDR register. The transmitter must write data to the HDR before transmit data and the receiver must read data from the HDR after receiving data. Receive acknowledge bit When the receiver wants to continue to receive the next data byte, it generates an acknowledge bit (TXAK) at the 9th clock. The transmitter checks the acknowledge bit (RXAK) to continue to write data to the I2C BUS or change to receive mode and dummy read the HDR register to release the SDA line and the master sends the STOP signal.

S C L S D A

Stop bit

S C L S D A

Start bit

S C L S D A S to p b it D a ta s ta b le D a ta a llo w c h a n g e

S ta r t b it

Data stable and data allow change

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HT46R23
T h e I C
2

B U S in itia l p r o g r a m

flo w

c h a r t a s fo llo w s :

I C B U S In itia l S ta r t

2

W r ite S la v e A d d re s s to H A D R

S E T H E N

D is a b le

I C B U S In te rru p t= ?

2

C L R E H I P o llin g H I. to g o to H -B U S IS R

E n a b le

S E T E H I W a it In te r r u p t G o to O th e r

G o to O th e r

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HT46R23
T h e I C B U S IS R p ro g ra m
2

flo w c h a r t a s fo llo w s :

IS R

S ta rt

N o H T X = 1 ?

H A S S = 1 ?

Y e s N o

R e a d . ro m H D R

Y e s

S R W = 1 ?

Y e s

N o

R E T I S E T H T X Y e s C L R C L R H T X T X A K

R X A K = 1 ? W r ite to H D R D u m m y R e a d . ro m H D R

C L R C L R

H T X T X A K

N o

W r ite to H D R R E T I D u m m y R e a d . ro m H D R R E T I

R E T I

R E T I

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HT46R23
ROM code option The following shows ten kinds of ROM code option in the HT46R23. ALL the ROM code options must be defined to ensure proper system function. No. 1 2 ROM Code Option OSC type selection. This option is to decide if an RC or crystal oscillator is chosen as system clock. WDT source selection. There are three types of selection: on-chip RC oscillator, instruction clock or disable the WDT. CLRWDT times selection. This option defines how to clear the WDT by instruction. ?One time? means that the CLR WDT instruction can clear the WDT. ?Two times? means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then WDT can be cleared. Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT. Pull-high selection. This option is to decide whether a pull-high resistance is visible or not in the input mode of the I/O ports. PA0~PA7, can be independently selected. PFD selection: PA3: level output or PFD output PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output WDT time-out period selection. There are four types of selection: WDT clock source divided by 212, 213, 214 and 215 Low voltage detector selection: Enable or disable LVD function. I2C BUS selection: PA6 and PA7: I/O or I2C BUS function

3

4 5 6

7

8 9 10

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Application Circuits
P A 0 ~ P A 2 P A 3 /P . D O S C 2 S e e b e lo w V
D D

O S C 1 O S C C ir c u it

P A 4 /T M R P A 5 /IN T P A 6 /S D A P A 7 /S C L

V D D 1 0 0 k W 0 .1 m . 1 0 k W R E S

H T 4 6 R 2 3

P C 0 ~ P C 4

0 .1 m . V S S

P B 0 /A N 0

P B 7 /A N 7 P D 0 /P W M 0 P D 1 /P W M 1

V R

D D

4 7 0 p .
O S C

O S C 1 fS
Y S /4

R C s y s te m o s c illa to r 3 0 k W < R O S C < 7 5 0 k W

O S C 2 O S C 1

C 1 O S C 2

C r y s ta l s y s te m o s c illa to r C 1 = C 2 = 3 0 0 p . , if fS Y S < 1 M H z O th e r w is e , C 1 = C 2 = 0

C 2

N o te : T h e r e s is ta n c e a n d c a p a c ita n c e fo r r e s e t c ir c u it s h o u ld b e d e s ig n e d to e n s u r e th a t th e V D D is s ta b le a n d r e m a in s in a v a lid r a n g e o f th e o p e r a tin g v o lta g e b e fo r e b r in g in g R E S to h ig h .

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HT46R23
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected

Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z

Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z

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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected

x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address ?: Flag is affected -: Flag is not affected
(1)

: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)

(2)

(3) (1) (4)

: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared. Otherwise the TO and PD flags remain unchanged.

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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 ? ADCM A,[m] Description Operation Affected flag(s) TC2 ? ADD A,[m] Description Operation Affected flag(s) TC2 ? ADD A,x Description Operation Affected flag(s) TC2 ? ADDM A,[m] Description Operation Affected flag(s) TC2 ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ? ACC+[m]+C

Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ? ACC+[m]+C

Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ? ACC+[m]

Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ? ACC+x

Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ? ACC+[m]

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AND A,[m] Description Operation Affected flag(s) TC2 ? AND A,x Description Operation Affected flag(s) TC2 ? ANDM A,[m] Description Operation Affected flag(s) TC2 ? CALL addr Description TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ? ACC ?AND? [m]

Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ? ACC ?AND? x

Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ? ACC ?AND? [m]

Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack ? PC+1 PC ? addr

Operation Affected flag(s)

TC2 ? CLR [m] Description Operation Affected flag(s) TC2 ?

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

Clear data memory The contents of the specified data memory are cleared to 0. [m] ? 00H

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

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CLR [m].i Description Operation Affected flag(s) TC2 ? CLR WDT Description Operation Affected flag(s) TC2 ? CLR WDT1 Description TC1 ? TO 0 PD 0 OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i ? 0

Clear Watchdog Timer The WDT and the WDT Prescaler are cleared (re-counting from 0). The power down bit (PD) and time-out bit (TO) are cleared. WDT and WDT Prescaler ? 00H PD and TO ? 0

Preclear Watchdog Timer The TO, PD flags, WDT and the WDT Prescaler has cleared (re-counting from 0), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT and WDT Prescaler ? 00H* PD and TO ? 0*

Operation Affected flag(s)

TC2 ? CLR WDT2 Description

TC1 ?

TO 0*

PD 0*

OV ?

Z ?

AC ?

C ?

Preclear Watchdog Timer The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting from 0), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT and WDT Prescaler ? 00H* PD and TO ? 0*

Operation Affected flag(s)

TC2 ? CPL [m] Description Operation Affected flag(s) TC2 ?

TC1 ?

TO 0*

PD 0*

OV ?

Z ?

AC ?

C ?

Complement data memory Each bit of the specified data memory is logically complemented (1?s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] ? [m]

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1?s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC ? [m]

Operation Affected flag(s)

TC2 ? DAA [m] Description

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 ? (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 ? (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ? ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ? ACC.7~ACC.4+AC1,C=C

Operation

Affected flag(s) TC2 ? DEC [m] Description Operation Affected flag(s) TC2 ? DECA [m] Description Operation Affected flag(s) TC2 ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ?

Decrement data memory Data in the specified data memory is decremented by 1. [m] ? [m]-1

Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC ? [m]-1

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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC ? PC+1 PD ? 1 TO ? 0

Operation

Affected flag(s) TC2 ? INC [m] Description Operation Affected flag(s) TC2 ? INCA [m] Description Operation Affected flag(s) TC2 ? JMP addr Description Operation Affected flag(s) TC2 ? MOV A,[m] Description Operation Affected flag(s) TC2 ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC ?addr TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO 0 PD 1 OV ? Z ? AC ? C ?

Increment data memory Data in the specified data memory is incremented by 1 [m] ? [m]+1

Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC ? [m]+1

Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC ? [m]

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MOV A,x Description Operation Affected flag(s) TC2 ? MOV [m],A Description Operation Affected flag(s) TC2 ? NOP Description Operation Affected flag(s) TC2 ? OR A,[m] Description Operation Affected flag(s) TC2 ? OR A,x Description Operation Affected flag(s) TC2 ? ORM A,[m] Description Operation Affected flag(s) TC2 ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? No operation No operation is performed. Execution continues with the next instruction. PC ? PC+1 TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC ? x

Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ?ACC

Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ? ACC ?OR? [m]

Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ? ACC ?OR? x

Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ?ACC ?OR? [m]

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RET Description Operation Affected flag(s) TC2 ? RET A,x Description Operation Affected flag(s) TC2 ? RETI Description Operation Affected flag(s) TC2 ? RL [m] Description Operation Affected flag(s) TC2 ? RLA [m] Description Operation Affected flag(s) TC2 ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC ? Stack

Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC ? Stack ACC ? x

Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC ? Stack EMI ? 1

Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) ? [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ? [m].7

Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) ? [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ? [m].7

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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) ? [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ? C C ? [m].7

Affected flag(s) TC2 ? RLCA [m] Description TC1 ? TO ? PD ? OV ? Z ? AC ? C ?

Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) ? [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ? C C ? [m].7

Operation

Affected flag(s) TC2 ? RR [m] Description Operation Affected flag(s) TC2 ? RRA [m] Description Operation Affected flag(s) TC2 ? RRC [m] Description Operation TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ?

Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i ? [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ? [m].0

Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) ? [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ? [m].0

Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i ? [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ? C C ? [m].0

Affected flag(s) TC2 ? Rev. 1.40 TC1 ? TO ? PD ? 36 OV ? Z ? AC ? C ? February 8, 2002

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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i ? [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ? C C ? [m].0

Operation

Affected flag(s) TC2 ? SBC A,[m] Description Operation Affected flag(s) TC2 ? SBCM A,[m] Description Operation Affected flag(s) TC2 ? SDZ [m] Description TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ?

Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ? ACC+[m]+C

Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ? ACC+[m]+C

Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ? ([m]-1)

Operation Affected flag(s)

TC2 ? SDZA [m] Description

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ? ([m]-1)

Operation Affected flag(s)

TC2 ?

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

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SET [m] Description Operation Affected flag(s) TC2 ? SET [m]. i Description Operation Affected flag(s) TC2 ? SIZ [m] Description TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? Set data memory Each bit of the specified data memory is set to 1. [m] ? FFH

Set bit of data memory Bit i of the specified data memory is set to 1. [m].i ? 1

Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ? ([m]+1)

Operation Affected flag(s)

TC2 ? SIZA [m] Description

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ? ([m]+1)

Operation Affected flag(s)

TC2 ? SNZ [m].i Description

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i?0

Operation Affected flag(s)

TC2 ?

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

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SUB A,[m] Description Operation Affected flag(s) TC2 ? SUBM A,[m] Description Operation Affected flag(s) TC2 ? SUB A,x Description Operation Affected flag(s) TC2 ? SWAP [m] Description Operation Affected flag(s) TC2 ? SWAPA [m] Description Operation Affected flag(s) TC2 ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ? ACC+[m]+1

Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ? ACC+[m]+1

Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ? ACC+x+1

Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 ? [m].7~[m].4

Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 ? [m].7~[m].4 ACC.7~ACC.4 ? [m].3~[m].0

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SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0

Operation Affected flag(s)

TC2 ? SZA [m] Description

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0

Operation Affected flag(s)

TC2 ? SZ [m].i Description

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0

Operation Affected flag(s)

TC2 ? TABRDC [m] Description Operation Affected flag(s) TC2 ? TABRDL [m] Description Operation Affected flag(s) TC2 ?

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ? ROM code (low byte) TBLH ? ROM code (high byte)

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ? ROM code (low byte) TBLH ? ROM code (high byte)

TC1 ?

TO ?

PD ?

OV ?

Z ?

AC ?

C ?

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XOR A,[m] Description Operation Affected flag(s) TC2 ? XORM A,[m] Description Operation Affected flag(s) TC2 ? XOR A,x Description Operation Affected flag(s) TC2 ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? TC1 ? TO ? PD ? OV ? Z ? AC ? C ? Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ? ACC ?XOR? [m]

Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ? ACC ?XOR? [m]

Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ? ACC ?XOR? x

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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright ? 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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