S2C Dual V-5 TAI LM Hardware Reference Manual


S2C Dual Virtex-5 TAI Logic Module
Reference Manual v1.11

S2C Inc.
1754 Technology Drive, Suite 206 San Jose, CA 95110-1320, USA Tel: +1 408 213 8818 Fax: +1 408 213 8821 www.s2cinc.com

Table of Contents
1. 2. Revision History........................................................................................1 Introduction ...............................................................................................2
2.1 2.2 2.3 General Features ...................................................................................................... 3 TAI-Compliant Hardware ........................................................................................... 4 Technical Support...................................................................................................... 5

3. 4.

Examining Contents..................................................................................6 Hardware Description ...............................................................................7
4.1 4.2 4.3 Hardware Specifications............................................................................................ 7 Hardware Components ............................................................................................. 8 Physical Dimensions ................................................................................................. 9 General Architecture................................................................................................ 10 Clock Architecture ................................................................................................... 10 IO Architecture......................................................................................................... 12 Setting Up Hardware ............................................................................................... 13 Adjusting Dedicated IO Voltage .............................................................................. 15 Downloading Hardware ........................................................................................... 17 System Requirements ............................................................................................. 18 Third-Party Software Requirements ........................................................................ 18 TAI Player Installation.............................................................................................. 18 License Management .............................................................................................. 22 7.4.1 Obtaining A License ................................................................................... 22 7.4.2 Registering the License.............................................................................. 22 7.4.3 Obtaining the Physical Address of the Ethernet Adapter ........................... 22 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 External Clock ............................................................................................ 23 Feedback Clock ......................................................................................... 24 Dedicated IO .............................................................................................. 26 Shared IO ................................................................................................... 35 SODIMM IO................................................................................................ 42 EXT Clock SMB.......................................................................................... 48 External IO (JX & JBX Connectors) ........................................................... 48 Safety Precautions ................................................................................... 50 Electrostatic Handling Considerations ..................................................... 50

5.

Hardware Architecture............................................................................10
5.1 5.2 5.3

6.

Hardware Setup.......................................................................................13
6.1 6.2 6.3

7.

TAI Player Runtime and Self-Testing .....................................................18
7.1 7.2 7.3 7.4

8.

External Connector Table .......................................................................23

9.

Mating Connectors and Cables..............................................................48
9.1.1 9.1.2 10.1.1 10.1.2

10. Care and Handling ..................................................................................50

11. Glossary...................................................................................................52

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

i

List of Figures
Figure 2-1 Figure 2-2 Figure 2-3 Figure 4-1 Figure 4-2 Figure 4-3 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 8-1 Figure 8-2 Figure 9-1 Figure 9-2 TAI Logic Module - Top View.................................................................................... 2 TAI Logic Module – Bottom View ............................................................................. 2 TAI-Compliant Logo ................................................................................................. 4 TAI Logic Module Major Components, Top View ..................................................... 8 TAI Logic Module Major Components, Bottom View................................................ 8 TAI Logic Module Physical Dimensions ................................................................... 9 TAI Logic Module General Architecture ................................................................. 10 TAI Logic Module External Clock Architecture....................................................... 11 TAI Logic Module Feedback Clock Architecture .................................................... 11 TAI Logic Module Dedicated IO Architecture ......................................................... 12 TAI Logic Module Shared IO Architecture.............................................................. 12 TAI Logic Module Spacer Installation..................................................................... 13 TAI Logic Module Setup Configuration .................................................................. 14 Lab Power Connector Pinout (JV2) ....................................................................... 14 Lab Power Connector Pinout (JV3) ....................................................................... 14 TAI Logic Module Switch Locations and Default Configuration (Top Side)............ 17 TAI Logic Module Switch Locations and Default Configuration (Bottom Side) ...... 17 TAI Player Setup Wizard........................................................................................ 18 TAI Player Setup Wizard – License Agreement..................................................... 19 TAI Player Setup Wizard – Choose Components.................................................. 19 TAI Player Setup Wizard – Install Location............................................................ 20 TAI Player Setup Wizard – Start Menu Folder ....................................................... 20 TAI Player Setup Wizard – Installing...................................................................... 21 TAI Player Setup Wizard – Finish .......................................................................... 21 Obtain the Physical Address .................................................................................. 22 TAI Logic Module External Connector Locations................................................... 23 TAI Logic Module External Connector Locations................................................... 23 Board Connection Methods ................................................................................... 48 TAI Logic Module JX Connector Spacing............................................................... 49

List of Tables
Table 4-1 Table 6-1 Table 6-2 Table 6-3 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 Table 8-6 Table 8-7 Functional Hardware Specifications......................................................................... 7 Switch-Dedicated IO Connector Linkage............................................................... 15 Dedicated IO Voltage Selection ............................................................................. 16 Switch Default Configuration.................................................................................. 16 External Clock Properties ...................................................................................... 24 Feedback Clock Properties.................................................................................... 25 Virtex-5 Pin Definitions........................................................................................... 26 Dedicated IO Connector Properties ....................................................................... 26 Shared IO Connector Properties............................................................................ 35 SODIMM Dedicated Pin Properties ....................................................................... 42 SODIMM2 Dedicated Pin Properties ..................................................................... 45

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

ii

1. Revision History
Version 1.11 Date 09/04/08 Notes Chapter8 :Modify Table 8-5 Chapter 4: Corrected Figure 4-2 1.10 07/01/08 Chapter 6: Corrected Figure 6-5 Chapter 8: Corrected the External Clock Properties Corrected Table 8-1 and Table 8-2 1.00 04/07/08 Initial release.

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

1

2. Introduction
The S2C Dual Virtex-5 TAI Logic Module is designed for rapid SoC/ASIC prototyping and support using TAI IP – a configurable FPGA-based IP format – to create designs in prototypes efficiently. One Dual Virtex-5 TAI Logic Module can hold designs with up to 6.6M ASIC gates and multiple TAI Logic Modules can be stacked together to accommodate designs requiring greater prototyping capacity. S2C's TAI Bus technology dynamically links the interconnections and debugging data of multiple TAI Logic Modules that are stacked together, allowing effortless compilation and debugging of complex designs. The highly expandable and reusable nature of TAI Logic Module makes it the most cost-effective method to build your SoC/ASIC prototypes. Figure 2-1 TAI Logic Module - Top View

Figure 2-2 TAI Logic Module – Bottom View

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

2

The Dual Virtex-5 TAI Logic Module is available in a hardware configurations: XC5VLX330. The XC5VLX330 model is equipped with two Xilinx Virtex-5 330 FPGAs and fits about 6.6 million ASIC gates. TAI Logic Module provides a number of prototyping benefits, allowing you to: Fully validate your SoC/ASIC designs using FPGA prototypes Start software and firmware development earlier in process using FPGA prototypes Shorten time-to-prototype by eliminating time-consuming roll-your-own FPGA prototypes Avoid operational risk from roll-your-own FPGA prototypes Lower costs versus building roll-your-own FPGA prototypes Stack multiple logic modules for designs requiring flexible size parameters Reuse multiple times Wield a number of optional features to enhance your design and verification results

2.1

General Features
The Dual Virtex-5 TAI Logic Module hardware’s general features are listed as follows: Capacity ? Up to 6.6M ASIC gates with two XC5VLX330 ? 20Mbits of FPGA internal memory with two XC5VLX330 Performance ? 500MHz clocking in single FPGA ? 400MHz differential FPGA to FPGA Advanced clock management ? Two on-board oscillator sockets ? Three pairs of differentials through SMB ? Three on-board programmable clock sources (1~200MHZ) ? 12 feedback clocks drawn from one of the two FPGAs or externally from a feedback line connector 720 dedicated external IOs ? Supports LVDS differential ? 360 IOs per FPGA 600 inter-FPGA connections ? Single-ended or LVDS differential ? Can be used as shared external IO ? Used as TAI Bus when multiple TAI Logic Modules are stacked Programmable IO settings ? Each dedicated IO socket can be separately set with four voltage settings ( 1.2V, 1.8V, 2.5V, and 3.3V) Single 12V voltage input FPGA configuration

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

3

? Automated configuration through USB interface from TAI Player runtime software ? JTAG interface for Xilinx download cable and ACE configure solution Self-test program ? TAI Player runtime software enable thorough self-test of all pins Battery back-up encryption key

2.2

TAI-Compliant Hardware
TAI Logic Module supports FPGA-based ESL design methodology using TAI IP – pre-compiled FPGA-based libraries – to perform system level design, validation, and SoC software development. S2C’s TAI Player software may also be purchased to enable the following TAI-compliant hardware features: Efficient system design creation of prototypes using TAI IP library Dynamic interconnection and debugging channels among multiple TAI Logic Modules through TAI Bus Automated compile and partition flow with easy-to-use GUI interface Global clock management Integrated logic and data analyzer among multiple FPGAs Support for the following verification modes: co-emulation, vector, and transaction-based co-modeling. All TAI-compliant hardware is affixed with the following label: Figure 2-3 TAI-Compliant Logo

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

4

2.3

Technical Support
The S2C technical support center is located in Shanghai, China. Please contact our technical support through one of the methods below. Please have your TAI Logic Module serial number ready when you contact us. The serial number is labeled on the lower right-hand corner of your TAI Logic Module. Telephone For live technical assistance, call our support hotline at +86 (21) 6120-2790 from 9:00 am to 6:00 pm (Beijing Time), Monday to Friday. Our support engineers speak English and Mandarin Chinese. Instant Messaging For real-time technical assistance, contact us through Windows Live Messenger or MSN messenger. Our support account name is support@s2cinc.com. Official support hours are from 9:00 am to 6:00 pm (Beijing Time), Monday to Friday – though we may also provide additional support during off-hours. E-mail You can also send any queries to our e-mail address: support@s2cinc.com. Our support staff will respond within one business day. In addition, ask your local sales channel about local support services available to you.

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

5

3. Examining Contents
The S2C Dual Virtex-5 TAI Logic Module package comprises the following components: One S2C Dual VIRTEX-5 TAI Logic Module One USB cable One 12V DC power adapter (Input AC220-110V; Output DC12V, 3A) One S2C I/O testing board One CD containing: ? ? S2C Dual V5 TAI Logic Module Reference Manual S2C TAI Player Install Programmer (runtime license only)

One printed Warranty Statement One printed Important Usage Notice

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

6

4. Hardware Description
4.1 Hardware Specifications
TAI Logic Module’s functional hardware specifications are described in the following table: Table 4-1 Functional Hardware Specifications
XC5VLX330-FF1760 12V 3.3V 0.8~3.3V 720 2 6 20 1320 140.0 mm X 260.0 mm 0.46 kg 12V DC 3A

FPGA Device Used Input Voltage Shared IO Voltage Dedicated IO Voltage Dedicated IO OSC Clock Input SMB Clock Input User Clocks Total Available IO Size Weight Power Supply Adapter

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

7

4.2

Hardware Components
Figure 4-1 TAI Logic Module Major Components, Top View

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

Dedicated IO

Figure 4-2 TAI Logic Module Major Components, Bottom View

8

Dedicated IO

4.3

Physical Dimensions
Figure 4-3 TAI Logic Module Physical Dimensions

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

9

5. Hardware Architecture
The Dual Virtex-5 TAI Logic Module’s hardware architecture is designed with both scalability and flexibility in mind. When only one TAI Logic Module is used, almost all IOs are brought out for maximum flexibility. When capacity expansion is needed, multiple TAI Logic Modules can be easily stacked through the shared IO connectors for scalability. In addition, the Virtex-5 TAI Logic Module also includes components that are reserved for the function interface, which enables advanced features such as dynamic interconnect bus technology, embedded integrated logic analyzer, powerful clock generations, co-emulation with simulators, and transaction-based co-modeling. This section illustrates TAI Logic Module’s general, clock, and IO architectures.

5.1

General Architecture
The general architecture of the basic system components and their connections are as follows: Figure 5-1 TAI Logic Module General Architecture

5.2

Clock Architecture
You can access 20 FPGA global clock nets from two oscillator sockets, three pairs of SMB input connectors, three CDCE706 clocks, and 12 IOs on the feedback line connectors. Both FPGAs, U1 and U2, have identical global clock IO pin assignments, which means that when a clock is connected to one of the 20 global clock lines on one of the FPGAs, the clock will also be

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

10

distributed to the same pin on the other FPGA. Figure 5-2 TAI Logic Module External Clock Architecture

You can also use the 12 feedback lines of internally generated clocks so that they can be routed to the global clock inputs of both FPGAs U1 and U2 with approximately the same timing. Without these feedback lines, clocks generated internally in one FPGA may cause large clock skews if the clocks are to be used in the other FPGA. In addition, the 12 feedback lines can also be used for asynchronous reset and other signals that require minimum skews between the two FPGAs. The 12 feedback lines are also connected to connector J1, enabling feedback clocks to output to other TAI Logic Module boards that are stacked on. The following diagram illustrates the architecture of the feedback lines. Figure 5-3 TAI Logic Module Feedback Clock Architecture

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

11

5.3

IO Architecture
TAI Logic Module contains two types of IOs: dedicated IOs and shared IOs. Dedicated IOs are connected to only one of the two FPGAs; each FPGA has 360 dedicated IOs by way of three 120-pin Samtec connectors. Shared IOs are connected to both FPGAs U1 and U2; there are a total of 600 such connections. Shared IOs are also used as inter-FPGA connections between FPGAs U1 and U2. The following diagram illustrates TAI Logic Module’s IO architecture. Figure 5-4 TAI Logic Module Dedicated IO Architecture

Figure 5-5 TAI Logic Module Shared IO Architecture

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

12

6. Hardware Setup
6.1 Setting Up Hardware
Setting up TAI Logic Module is simple and straightforward. First, fit a black spacer at each corner of the TAI Logic Module. As the black spacers — insulated in plastic to avoid electrical contact — are connected to the ground plane, do not place the TAI Logic Module on the conducting plane. Also, two white spacers are available for installation on the top and bottom center holes. Use the white spacers only when you are transmitting 12V of power. Figure 6-1 TAI Logic Module Spacer Installation

After the black spacers are fitted, connect the 12V DC power adapter to TAI Logic Module and then plug the adapter to a power outlet. The power adapter supports up to 3A of current. Once TAI Logic Module is powered on, the power status LED1 will light up. LED7 will also light up to indicate that the board temperature is in a normal state. A blinking LED7 indicates that the board temperature is too high and must be reduced to continue normal operation. Should the blinking persist, please contact S2C Support. Please note that when the FPGA is work, the temperature may rise. The FPGA may be damaged. Please take care of V5 over heating and contact S2C Support, we will give you our solutions.

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

13

Figure 6-2 TAI Logic Module Setup Configuration

If your design requires a target board, it can be directly mounted onto TAI Logic Module or connected through a Samtec 120-pin cable (refer to Figure 8-1 TAI Logic Module External Connector Locations for more details).

TAI Logic Module provides 4 power sources for target boards from 2 Lab Power Connectors. Each Lab Power Connector provides 2 adjustable power sources. The voltage of the power sources will be the same with the corresponding IO connector as indicated in Figure 6-3 and Figure 6-4. To adjust the voltages of the 4 power sources, please refer to section 6.2 for adjusting voltage for the corresponding IO connectors. Figure 6-3 Lab Power Connector Pinout (JV2)

Figure 6-4

Lab Power Connector Pinout (JV3)

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

14

NOTES: (i) Do not attach the 12V voltage though the lab power connectors on your TAI Logic Module. This may damage your TAI Logic Module. If you are not sure whether they have been set properly, please contact S2C Support before making any adjustments. (ii) You can draw output voltage to work with an external device or daughter board through the lab power connectors on your TAI Logic Module. When you draw voltage from Pin 1 or Pin 3 of the lab power connector, you should connect Pin 2 of the lab power connector to ground. For the voltage setting of the Samtec connectors (J3, J4, J9, and J10), please refer to the Table 6.2 Adjusting Dedicated IO Voltage.

6.2

Adjusting Dedicated IO Voltage
All 720 dedicated IO voltages can be easily adjusted to 1.2V, 1.8V, 2.5V, or 3.3V by adjusting the module’s switches. FPGA U1 has 360 dedicated IOs that can be accessed from IO connectors J9, J10, and J12; FPGA U2 has 360 dedicated IOs that can be accessed from IO connectors J3, J4, and J7. The dedicated IOs are separated into six power regions, each controlled by one of six switches (S1, S2, S6, S9, S10, and S11). Table 6-1 indicates the dedicated IOs controlled by each of the eight jumpers. Table 6-1 Switch-Dedicated IO Connector Linkage
FPGA IO Bank U1 Bank 17/21/25 U1 Bank 18/22/26 U1 Bank 11/13/15 U2 Bank 17/21/25 U2 Bank 18/22/26 U2 Bank 11/13/15 IO Connector J10 J9 J12 J4 J3 J7

Switch S6 S9 S10 S1 S2 S11

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

15

The user-defined voltage can be easily set to 1.2V, 1.8V, 2.5V, or 3.3V by turning on the switches of S1, S2, S6, S9, S10, and S11. The switch settings for these four voltage levels are as table 6-2 Table 6-2
Voltage 1.2V 1.8V 2.5V 3.3V

Dedicated IO Voltage Selection
Switch Settings Pin4 ON (All other pins OFF) Pin3 ON (All other pins OFF) Pin2 ON (All other pins OFF) Pin1 ON (All other pins OFF)

Aside from the four voltage levels listed above, TAI Logic Module can support any user-defined dedicated IO voltage from 1.2V to 3.3V by adjusting some of the on-board resistors. If a specific voltage beyond the four voltages listed in Table 6-3 is needed, please contact our technical support engineers for assistance. Table 6-3 displays the default configuration for all switches. Table 6-3
Switch S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15

Switch Default Configuration
Pin 1 ON ON ON OFF OFF ON ON ON ON ON ON OFF OFF OFF OFF Pin 2 OFF OFF ON ON ON OFF OFF OFF OFF OFF OFF ON OFF OFF OFF Pin 3 OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Pin 4 OFF OFF OFF ON ON OFF OFF OFF OFF OFF OFF ON OFF OFF OFF

Please do not change the default value for the following switch: The following two figures illustrate the location of every switch and OSC on the top and bottom side of TAI Logic Module, respectively, to illustrate relative pin positioning.

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

16

Figure 6-5 TAI Logic Module Switch Locations and Default Configuration (Top Side)

Figure 6-6 TAI Logic Module Switch Locations and Default Configuration (Bottom Side)

6.3

Downloading Hardware
You can download the design file onto FPGA using a USB cable from TAI Player Runtime Software or using Xilinx Download cable. For downloading using USB cable, please refer to Chapter 7.2. For downloading using Xilinx Download cable, plug the Xilinx Download cable on to JTAG connector J16 and refer to Xilinx documentation. When the download is complete, LED2, LED3, and LED6 will light up. Refer to Figure 6-2 for the positioning of the LEDs.

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

17

7. TAI Player Runtime and Self-Testing
7.1 System Requirements
CPU: Memory: Disk Space: x86 series, 500MHz or higher, 2GHz is recommended. 512M, 1G or more is recommended. At least 200M bytes to install the software and firmware. (The majority of required disk space is occupied by working projects and not by the application itself.) OS: Microsoft Windows XP

7.2

Third-Party Software Requirements
EDA Tools: Xilinx ISE (mandatory) and Synplicity Synplify or Synplify Pro (optional).

7.3

TAI Player Installation
The installation process is illustrated in a step-by-step manner as follows: Start up the installation executable and the Installation Wizard window will appear as follows: Figure 7-1 TAI Player Setup Wizard

Press Next, and a license agreement page will be showed:

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

18

Figure 7-2 TAI Player Setup Wizard – License Agreement

Read the license agreement carefully and press I Agree to continue the installation process or Cancel to quit.

In the Choose Components window, leave the default parameters as is and click Next to proceed. Figure 7-3 TAI Player Setup Wizard – Choose Components

Now in the Choose Installation Location window, select the destination path you wish to save the TAI Player program in by using the Browse button, or simply click on Next to install into the
Dual Virtex-5 TAI Logic Module Reference Manual v1.11

19

default directory. Figure 7-4 TAI Player Setup Wizard – Install Location

In the Choose Start Menu Folder window, click Install to begin program installation. Figure 7-5 TAI Player Setup Wizard – Start Menu Folder

We recommended that you leave the default parameters as is and directly start the file extraction process. The Install Wizard will extract the program contents into pre-specified directories:

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

20

Figure 7-6 TAI Player Setup Wizard – Installing

After the files are extracted, press Finish to complete the installation. Figure 7-7 TAI Player Setup Wizard – Finish

Now you can start TAI Player from the Windows Start menu. If you cannot activate the program, please refer to Section 2.4: License Management.

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

21

7.4

License Management
TAI Player software is protected by a usage license to ensure that access is provided only to legitimate users. License rights can range from singular use with one specific TAI Logic Module type all the way to a universal use AP-COMPILE license that permits access to all TAI Logic Module types.

7.4.1
1.

Obtaining A License

TAI Player’s license is bound to the physical address of an Ethernet adapter. So, first ascertain that you have at least one Ethernet card installed on your computer. Then, obtain the card’s physical address (please refer to Section 2.4.3: Obtaining the Physical Address of the Ethernet Adapter). If there is more than one Ethernet card on your computer, select the card of your choice and use its physical address.

2.

Contact S2C’s Technical Support team through the contact information provided in Section 1.4: Technical Support and send them the physical address of your computer’s Ethernet adapter. The address should be a six-byte (48-bit) hex digit separated by dashes, such as: 00-F6-D4-56-28-9A.

3.

Our Technical Support team will then promptly send a license file that will unlock TAI Player’s license key.

7.4.2

Registering the License

After obtaining the license file, copy it into the installation directory that you selected during the installation process (please refer to Section 2.3: TAI Player Installation). You can now start TAI Player from the Windows Start menu.

7.4.3

Obtaining the Physical Address of the Ethernet Adapter

There are several ways to obtain the Ethernet adapter’s physical address. A relatively simple way is to open a console window, and enter in the command IPCONFIG –all to find the address, as shown in the figure below: Figure 7-8 Obtain the Physical Address

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

22

8.

External Connector Table
TAI Logic Module has four connector groups, classified as external clock, feedback clock, dedicated IO, and shared IO. This section provides the relationship between the various connectors and their corresponding FPGA pinouts. The following diagram illustrates the location of the external connectors. Figure 8-1 TAI Logic Module External Connector Locations

The J1 to J12 Samtec connectors on TAI Logic Module have pin orientations corresponding to the layout indicated in the figure below. Figure 8-2 TAI Logic Module External Connector Locations

8.1.1

External Clock

A total of 20 external clocks can be input from two oscillator sockets, 3 pairs of SMB connectors, 3 on-board programmable clock sources and 12 IOs on the J1 feedback line connector. These 20 external clocks are routed to the 20 global clock lines of both FPGA U1 and U2. The following table provides the exact FPGA pin locations of the 20 external clocks. Note that the global clock pin locations for U1 and U2 are identical.

NOTES: (i) Do not remove the 48MHz Oscillator installed on OSC3. The 48MHz Oscillator is required for operating the Dual Virtex-5 TAI Logic Module

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

23

Table 8-1
Ext Clock CDCE706(1) CDCE706(2) CDCE706(3) OSC1 OSC2 JG1 JG2 JG3 FB Clock1 FB Clock2 FB Clock3 FB Clock4 FB Clock5 FB Clock6 FB Clock7 FB Clock8 FB Clock9 FB Clock10 FB Clock11 FB Clock12

External Clock Properties
U1 Pin Clock K15 M27 K13 L27 L15 K28 M14 J30 N16 L29 AK28 AL16 AM29 AN16 AP30 AM13 AM28 AN15 AL27 AP13 U2 Pin Clock K15 M27 K13 L27 L15 K28 M14 J30 N16 L29 AK28 AL16 AM29 AN16 AP30 AM13 AM28 AN15 AL27 AP13 Connector Location U9.11 U9.15 U9.19 OSC1.3 OSC2.3 JG1.1 JG2.1 JG3.1 J1.120 J1.118 J1.116 J1.114 J1.112 J1.110 J1.108 J1.106 J1.104 J1.102 J1.100 J1.098

8.1.2

Feedback Clock

One Dual Virtex-5 TAI Logic Module provides 12 feedback clock lines for FPGA internally generated signals, such as clocks and asynchronous resets, which require routing back to the FPGA global clock nets. Using the feedback clock lines will minimize the clock skew between the two FPGAs. To use these feedback lines, assign the output of the internally generated signal to the specified pin location according to the table below. All 12 feedback clocks also output to connector J1.

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

24

Please note that the feedback lines are shared between U1 and U2, meaning that only one FPGA can use a specific feedback line at one time. The feedback lines are also accessible from connector J1, which can be used to route the feedback clocks to other boards stacked on the TAI Logic Module. Feedback clocks can also be used as inter-FPGA connections and shared IO, so make sure to avoid conflicts when assigning signals to the feedback lines. Table 8-2
Feedback Clock 01 02 03 04 05 06 07 08 09 10 11 12

Feedback Clock Properties
Top CON J1.120 J1.118 J1.116 J1.114 J1.112 J1.110 J1.108 J1.106 J1.104 J1.102 J1.100 J1.098 Bottom CON JB1.120 JB1.118 JB1.116 JB1.114 JB1.112 JB1.110 JB1.108 JB1.106 JB1.104 JB1.102 JB1.100 JB1.098 FPGA Feed Clock Out U1 U1.Y32 U1.AA32 U1.Y33 U1.W32 U1.V33 U1.W33 U1.V35 U1.V34 U1.U36 U1.V36 U1.U34 U1.T35 U2 U2.Y32 U2.AA32 U2.Y33 U2.W32 U2.V33 U2.W33 U2.V35 U2.V34 U2.U36 U2.V36 U2.U34 U2.T35 FPGA Feed Clock In U1 U1.N16 U1.L29 U1.AK28 U1.AL16 U1.AM29 U1.AN16 U1.AP30 U1.AM13 U1.AM28 U1.AN15 U1.AL27 U1.AP13 U2 U2.N16 U2.L29 U2.AK28 U2.AL16 U2.AM29 U2.AN16 U2.AP30 U2.AM13 U2.AM28 U2.AN15 U2.AL27 U2.AP13

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

25

8.1.3

Dedicated IO

Dedicated IO connectors are those labeled J3, J4, J7, J9, J10, and J12. They are used to connect TAI Logic Module to target board and peripheral extensions. Every IO is directly wire-linked to one FPGA IO pin. Pin connections J3 to U2 are identical to J9 to U1, and pin connections J4 to U2 are identical to J10 to U1. The dedicated IOs support different Xilinx IO standards as described in Table 7-3. Table 8-3
Pin Name User IO Pins All user IO pins are capable of differential signalling and can implement LVDS, LVDSEXT, ULVDS, BLVDS, LVPECL, or LDT pairs. Each user IO is IO_LXXY_# Input/Output labeled “IO_LXXY_#”, where: IO indicates a user IO pin. LXXY indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair. # indicates the FPGA Bank number. Multi-Function Pins IO_LXXY_ZZZ_# Multi-function pins are labelled “IO_LXXY_ZZZ_#”, where ZZZ represents one or more of the functions described below. ADC1 through ADC7 input pins are reserved for future use but can be used for IO or other designated functions. These lower capacitance clock pins connect to Clock Capable IOs and can CC LC SMn Input/Output Input/Output Input/Output be used as LVDS clock inputs. These pins do not support LVDS outputs, and they become regular user IOs when not needed for clocks. These lower capacitance pins do not support LVDS outputs. SM1 through SM7 input pins are reserved for future use but can be used for IO or other designated functions. These are the input threshold voltage pins. Each input threshold voltage pin VREF Input/Output IO_XXY_REF_# sets the reference voltage for the nearby seven pins from IO_(XX - 4)Y_# to IO_(XX + 3)Y_#. These pins become user IOs when an external threshold voltage is not needed. VRN VRP Input/Output Input/Output This pin is for the DCI voltage reference resistor of N transistor (per bank, to be pulled High with reference resistor). This pin is for the DCI voltage reference resistor of P transistor (per bank, to be pulled Low with reference resistor).

Virtex-5 Pin Definitions
Direction Description

For a given multi-function pin, ZZZ is one or more of the following: ADCn Input/Output

The following table shows the connections of all dedicated IO connector pins and their corresponding FPGA pins. Table 8-4 Dedicated IO Connector Properties
J3 (Odd Pins) Top Con J3.001 J3.003 J3.005 J3.007 J3.009 Bottom Con JB3.001 JB3.003 JB3.005 JB3.007 JB3.009 FPGA IO Pin U2.AJ11 U2.AJ10 U2.AL10 U2.AK10 U2.AM11 IO Description IO_L18N_26 IO_L18P_26 IO_L17N_26 IO_L17P_26 IO_L15N_26 Top Con J3.002 J3.004 J3.006 J3.008 J3.010 Bottom Con JB3.002 JB3.004 JB3.006 JB3.008 JB3.010 J3 (Even Pins) FPGA IO Pin U2.AK12 U2.AJ12 U2.AL12 U2.AL11 U2.AP10 IO Description IO_L19N_26 IO_L19P_26 IO_L16N_26 IO_L16P_26 IO_L14N_VREF_26

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

26

J3 (Odd Pins) Top Con J3.011 J3.013 J3.015 J3.017 J3.019 J3.021 J3.023 J3.025 J3.027 J3.029 J3.031 J3.033 J3.035 J3.037 J3.039 J3.041 J3.043 J3.045 J3.047 J3.049 J3.051 J3.053 J3.055 J3.057 J3.059 J3.061 J3.063 J3.065 J3.067 J3.069 J3.071 J3.073 J3.075 J3.077 J3.079 J3.081 J3.083 J3.085 J3.087 J3.089 J3.091 J3.093 J3.095 J3.097 J3.099 J3.101 J3.103 J3.105 J3.107 J3.109 Bottom Con JB3.011 JB3.013 JB3.015 JB3.017 JB3.019 JB3.021 JB3.023 JB3.025 JB3.027 JB3.029 JB3.031 JB3.033 JB3.035 JB3.037 JB3.039 JB3.041 JB3.043 JB3.045 JB3.047 JB3.049 JB3.051 JB3.053 JB3.055 JB3.057 JB3.059 JB3.061 JB3.063 JB3.065 JB3.067 JB3.069 JB3.071 JB3.073 JB3.075 JB3.077 JB3.079 JB3.081 JB3.083 JB3.085 JB3.087 JB3.089 JB3.091 JB3.093 JB3.095 JB3.097 JB3.099 JB3.101 JB3.103 JB3.105 JB3.107 JB3.109 FPGA IO Pin U2.AM12 U2.AN10 U2.AM9 U2.AP12 U2.AP11 U2.AU11 U2.AV11 U2.AR10 U2.AR9 U2.AT9 U2.AU9 U2.AR8 U2.AR7 U2.AU7 U2.AV6 U2.AF12 U2.AG12 U2.AE10 U2.AF11 U2.AF9 U2.AF10 U2.AG9 U2.AH10 U2.AG8 U2.AH8 U2.AK9 U2.AL9 U2.AM8 U2.AN8 U2.AP6 U2.AP7 U2.AT6 U2.AT5 U2.AV4 U2.AV5 U2.AC11 U2.AB11 U2.AB9 U2.AB8 U2.AB7 U2.AC8 U2.AE7 U2.AD6 U2.AF5 U2.AF6 U2.AH6 U2.AG6 U2.AG4 U2.AH4 U2.AL5 IO Description IO_L15P_26 IO_L13N_26 IO_L13P_26 IO_L11N_CC_26 IO_L11P_CC_26 IO_L7N_26 IO_L7P_26 IO_L9N_CC_26 IO_L9P_CC_26 IO_L4N_VREF_26 IO_L4P_26 IO_L3N_26 IO_L3P_26 IO_L0N_26 IO_L0P_26 IO_L8N_CC_22 IO_L8P_CC_22 IO_L0N_22 IO_L0P_22 IO_L2N_22 IO_L2P_22 IO_L7N_22 IO_L7P_22 IO_L4N_VREF_22 IO_L4P_22 IO_L11N_CC_22 IO_L11P_CC_22 IO_L13N_22 IO_L13P_22 IO_L15N_22 IO_L15P_22 IO_L18N_22 IO_L18P_22 IO_L16N_22 IO_L16P_22 IO_L0N_18 IO_L0P_18 IO_L3N_18 IO_L3P_18 IO_L4N_VREF_18 IO_L4P_18 IO_L6N_18 IO_L6P_18 IO_L9N_CC_18 IO_L9P_CC_18 IO_L10N_CC_18 IO_L10P_CC_18 IO_L11N_CC_18 IO_L11P_CC_18 IO_L14N_VREF_18 Top Con J3.012 J3.014 J3.016 J3.018 J3.020 J3.022 J3.024 J3.026 J3.028 J3.030 J3.032 J3.034 J3.036 J3.038 J3.040 J3.042 J3.044 J3.046 J3.048 J3.050 J3.052 J3.054 J3.056 J3.058 J3.060 J3.062 J3.064 J3.066 J3.068 J3.070 J3.072 J3.074 J3.076 J3.078 J3.080 J3.082 J3.084 J3.086 J3.088 J3.090 J3.092 J3.094 J3.096 J3.098 J3.100 J3.102 J3.104 J3.106 J3.108 J3.110 Bottom Con JB3.012 JB3.014 JB3.016 JB3.018 JB3.020 JB3.022 JB3.024 JB3.026 JB3.028 JB3.030 JB3.032 JB3.034 JB3.036 JB3.038 JB3.040 JB3.042 JB3.044 JB3.046 JB3.048 JB3.050 JB3.052 JB3.054 JB3.056 JB3.058 JB3.060 JB3.062 JB3.064 JB3.066 JB3.068 JB3.070 JB3.072 JB3.074 JB3.076 JB3.078 JB3.080 JB3.082 JB3.084 JB3.086 JB3.088 JB3.090 JB3.092 JB3.094 JB3.096 JB3.098 JB3.100 JB3.102 JB3.104 JB3.106 JB3.108 JB3.110

J3 (Even Pins) FPGA IO Pin U2.AN11 U2.AP8 U2.AN9 U2.AT12 U2.AR12 U2.AU12 U2.AU13 U2.AT11 U2.AT10 U2.AV9 U2.AV10 U2.AU6 U2.AT7 U2.AV8 U2.AU8 U2.AG11 U2.AH11 U2.AE8 U2.AE9 U2.AF7 U2.AG7 U2.AJ8 U2.AH9 U2.AK7 U2.AJ7 U2.AL7 U2.AK8 U2.AN6 U2.AM7 U2.AP5 U2.AR5 U2.AT4 U2.AU4 U2.AU3 U2.AV3 U2.AD10 U2.AD11 U2.AC9 U2.AC10 U2.AD8 U2.AD7 U2.AE5 U2.AD5 U2.AF4 U2.AE4 U2.AH5 U2.AJ6 U2.AK4 U2.AJ5 U2.AL4 IO Description IO_L14P_26 IO_L12N_VRP_26 IO_L12P_VRN_26 IO_L10N_CC_26 IO_L10P_CC_26 IO_L6N_26 IO_L6P_26 IO_L8N_CC_26 IO_L8P_CC_26 IO_L5N_26 IO_L5P_26 IO_L2N_26 IO_L2P_26 IO_L1N_26 IO_L1P_26 IO_L9N_CC_22 IO_L9P_CC_22 IO_L1N_22 IO_L1P_22 IO_L3N_22 IO_L3P_22 IO_L6N_22 IO_L6P_22 IO_L5N_22 IO_L5P_22 IO_L10N_CC_22 IO_L10P_CC_22 IO_L12N_VRP_22 IO_L12P_VRN_22 IO_L14N_VREF_22 IO_L14P_22 IO_L17N_22 IO_L17P_22 IO_L19N_22 IO_L19P_22 IO_L1N_18 IO_L1P_18 IO_L2N_18 IO_L2P_18 IO_L7N_18 IO_L7P_18 IO_L5N_18 IO_L5P_18 IO_L8N_CC_18 IO_L8P_CC_18 IO_L13N_18 IO_L13P_18 IO_L12N_VRP_18 IO_L12P_VRN_18 IO_L15N_18

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

27

J3 (Odd Pins) Top Con J3.111 J3.113 J3.115 J3.117 J3.119 Bottom Con JB3.111 JB3.113 JB3.115 JB3.117 JB3.119 FPGA IO Pin U2.AL6 U2.AN5 U2.AM6 U2.AN3 U2.AP3 IO Description IO_L14P_18 IO_L19N_18 IO_L19P_18 IO_L16N_18 IO_L16P_18 Top Con J3.112 J3.114 J3.116 J3.118 J3.120 Bottom Con JB3.112 JB3.114 JB3.116 JB3.118 JB3.120

J3 (Even Pins) FPGA IO Pin U2.AK5 U2.AM4 U2.AN4 U2.AR4 U2.AR3 IO Description IO_L15P_18 IO_L17N_18 IO_L17P_18 IO_L18N_18 IO_L18P_18

J4 (Odd Pins) Top Con J4.001 J4.003 J4.005 J4.007 J4.009 J4.011 J4.013 J4.015 J4.017 J4.019 J4.021 J4.023 J4.025 J4.027 J4.029 J4.031 J4.033 J4.035 J4.037 J4.039 J4.041 J4.043 J4.045 J4.047 J4.049 J4.051 J4.053 J4.055 J4.057 J4.059 J4.061 J4.063 J4.065 J4.067 J4.069 J4.071 J4.073 J4.075 J4.077 Bottom Con JB4.001 JB4.003 JB4.005 JB4.007 JB4.009 JB4.011 JB4.013 JB4.015 JB4.017 JB4.019 JB4.021 JB4.023 JB4.025 JB4.027 JB4.029 JB4.031 JB4.033 JB4.035 JB4.037 JB4.039 JB4.041 JB4.043 JB4.045 JB4.047 JB4.049 JB4.051 JB4.053 JB4.055 JB4.057 JB4.059 JB4.061 JB4.063 JB4.065 JB4.067 JB4.069 JB4.071 JB4.073 JB4.075 JB4.077 FPGA IO Pin U2.AT40 U2.AR40 U2.AP40 U2.AN40 U2.AM38 U2.AN38 U2.AL37 U2.AM37 U2.AK39 U2.AJ38 U2.AH38 U2.AJ37 U2.AF37 U2.AG37 U2.AD38 U2.AE37 U2.AD35 U2.AC36 U2.AB36 U2.AC35 U2.AU37 U2.AU38 U2.AT36 U2.AR37 U2.AN36 U2.AP35 U2.AM34 U2.AN34 U2.AK34 U2.AL34 U2.AK35 U2.AJ35 U2.AG34 U2.AH34 U2.AF34 U2.AF36 U2.AE32 U2.AD33 U2.AB32 IO Description IO_L9N_CC_17 IO_L9P_CC_17 IO_L8N_CC_17 IO_L8P_CC_17 IO_L18N_17 IO_L18P_17 IO_L19N_17 IO_L19P_17 IO_L13N_17 IO_L13P_17 IO_L15N_17 IO_L15P_17 IO_L7N_17 IO_L7P_17 IO_L4N_VREF_17 IO_L4P_17 IO_L2N_17 IO_L2P_17 IO_L1N_17 IO_L1P_17 IO_L5N_21 IO_L5P_21 IO_L7N_21 IO_L7P_21 IO_L13N_21 IO_L13P_21 IO_L15N_21 IO_L15P_21 IO_L19N_21 IO_L19P_21 IO_L17N_21 IO_L17P_21 IO_L10N_CC_21 IO_L10P_CC_21 IO_L8N_CC_21 IO_L9N_CC_21 IO_L2N_21 IO_L2P_21 IO_L0N_21 Top Con J4.002 J4.004 J4.006 J4.008 J4.010 J4.012 J4.014 J4.016 J4.018 J4.020 J4.022 J4.024 J4.026 J4.028 J4.030 J4.032 J4.034 J4.036 J4.038 J4.040 J4.042 J4.044 J4.046 J4.048 J4.050 J4.052 J4.054 J4.056 J4.058 J4.060 J4.062 J4.064 J4.066 J4.068 J4.070 J4.072 J4.074 J4.076 J4.078 Bottom Con JB4.002 JB4.004 JB4.006 JB4.008 JB4.010 JB4.012 JB4.014 JB4.016 JB4.018 JB4.020 JB4.022 JB4.024 JB4.026 JB4.028 JB4.030 JB4.032 JB4.034 JB4.036 JB4.038 JB4.040 JB4.042 JB4.044 JB4.046 JB4.048 JB4.050 JB4.052 JB4.054 JB4.056 JB4.058 JB4.060 JB4.062 JB4.064 JB4.066 JB4.068 JB4.070 JB4.072 JB4.074 JB4.076 JB4.078

J4 (Even Pins) FPGA IO Pin U2.AU39 U2.AV40 U2.AR39 U2.AT39 U2.AP38 U2.AN39 U2.AM39 U2.AL39 U2.AK37 U2.AK38 U2.AH39 U2.AG39 U2.AG38 U2.AF39 U2.AE38 U2.AE39 U2.AD37 U2.AD36 U2.AC34 U2.AB34 U2.AV38 U2.AV39 U2.AR38 U2.AT37 U2.AP36 U2.AP37 U2.AN35 U2.AM36 U2.AL35 U2.AL36 U2.AJ36 U2.AH36 U2.AG36 U2.AH35 U2.AE35 U2.AF35 U2.AE34 U2.AE33 U2.AD32 IO Description IO_L10N_CC_17 IO_L10P_CC_17 IO_L11N_CC_17 IO_L11P_CC_17 IO_L17N_17 IO_L17P_17 IO_L16N_17 IO_L16P_17 IO_L14N_VREF_17 IO_L14P_17 IO_L12N_VRP_17 IO_L12P_VRN_17 IO_L6N_17 IO_L6P_17 IO_L5N_17 IO_L5P_17 IO_L3N_17 IO_L3P_17 IO_L0N_17 IO_L0P_17 IO_L4N_VREF_21 IO_L4P_21 IO_L6N_21 IO_L6P_21 IO_L12N_VRP_21 IO_L12P_VRN_21 IO_L14N_VREF_21 IO_L14P_21 IO_L18N_21 IO_L18P_21 IO_L16N_21 IO_L16P_21 IO_L11N_CC_21 IO_L11P_CC_21 IO_L8P_CC_21 IO_L9P_CC_21 IO_L3N_21 IO_L3P_21 IO_L1N_21

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

28

J4 (Odd Pins) Top Con J4.079 J4.081 J4.083 J4.085 J4.087 J4.089 J4.091 J4.093 J4.095 J4.097 J4.099 J4.101 J4.103 J4.105 J4.107 J4.109 J4.111 J4.113 J4.115 J4.117 J4.119 Bottom Con JB4.079 JB4.081 JB4.083 JB4.085 JB4.087 JB4.089 JB4.091 JB4.093 JB4.095 JB4.097 JB4.099 JB4.101 JB4.103 JB4.105 JB4.107 JB4.109 JB4.111 JB4.113 JB4.115 JB4.117 JB4.119 FPGA IO Pin U2.AB33 U2.AT35 U2.AU36 U2.AT34 U2.AU34 U2.AR34 U2.AR35 U2.AT31 U2.AT32 U2.AP32 U2.AR32 U2.AN31 U2.AP31 U2.AM31 U2.AL31 U2.AK32 U2.AJ32 U2.AJ31 U2.AH31 U2.AF31 U2.AG31 IO Description IO_L0P_21 IO_L5N_25 IO_L5P_25 IO_L6N_25 IO_L6P_25 IO_L7N_25 IO_L7P_25 IO_L11N_CC_25 IO_L11P_CC_25 IO_L13N_25 IO_L13P_25 IO_L12N_VRP_25 IO_L12P_VRN_25 IO_L19N_25 IO_L19P_25 IO_L17N_25 IO_L17P_25 IO_L3N_25 IO_L3P_25 IO_L0N_25 IO_L0P_25 Top Con J4.080 J4.082 J4.084 J4.086 J4.088 J4.090 J4.092 J4.094 J4.096 J4.098 J4.100 J4.102 J4.104 J4.106 J4.108 J4.110 J4.112 J4.114 J4.116 J4.118 J4.120 Bottom Con JB4.080 JB4.082 JB4.084 JB4.086 JB4.088 JB4.090 JB4.092 JB4.094 JB4.096 JB4.098 JB4.100 JB4.102 JB4.104 JB4.106 JB4.108 JB4.110 JB4.112 JB4.114 JB4.116 JB4.118 JB4.120

J4 (Even Pins) FPGA IO Pin U2.AC33 U2.AV36 U2.AV35 U2.AV34 U2.AV33 U2.AU33 U2.AU32 U2.AU31 U2.AV31 U2.AP33 U2.AR33 U2.AM33 U2.AN33 U2.AM32 U2.AL32 U2.AJ33 U2.AK33 U2.AG32 U2.AH33 U2.AG33 U2.AF32 IO Description IO_L1P_21 IO_L4N_VREF_25 IO_L4P_25 IO_L9N_CC_25 IO_L9P_CC_25 IO_L8N_CC_25 IO_L8P_CC_25 IO_L10N_CC_25 IO_L10P_CC_25 IO_L14N_VREF_25 IO_L14P_25 IO_L15N_25 IO_L15P_25 IO_L18N_25 IO_L18P_25 IO_L16N_25 IO_L16P_25 IO_L2N_25 IO_L2P_25 IO_L1N_25 IO_L1P_25

J7 (Odd Pins) Top Con J7.001 J7.003 J7.005 J7.007 J7.009 J7.011 J7.013 J7.015 J7.017 J7.019 J7.021 J7.023 J7.025 J7.027 J7.029 J7.031 J7.033 J7.035 J7.037 J7.039 J7.041 J7.043 J7.045 J7.047 J7.049 Bottom Con JB7.001 JB7.003 JB7.005 JB7.007 JB7.009 JB7.011 JB7.013 JB7.015 JB7.017 JB7.019 JB7.021 JB7.023 JB7.025 JB7.027 JB7.029 JB7.031 JB7.033 JB7.035 JB7.037 JB7.039 JB7.041 JB7.043 JB7.045 JB7.047 JB7.049 FPGA IO Pin U2.G41 U2.F41 U2.J41 U2.H41 U2.L41 U2.L40 U2.P40 U2.N40 U2.R40 U2.P41 U2.T41 U2.T40 U2.W41 U2.V40 U2.AA41 U2.AA42 U2.AA39 U2.AA40 U2.AA37 U2.Y37 U2.F40 U2.F39 U2.H39 U2.H38 U2.K39 IO Description IO_L1N_11 IO_L1P_11 IO_L2N_11 IO_L2P_11 IO_L4N_VREF_11 IO_L4P_11 IO_L7N_11 IO_L7P_11 IO_L13N_11 IO_L13P_11 IO_L14N_VREF_11 IO_L14P_11 IO_L17N_SM11N_11 IO_L17P_SM11P_11 IO_L19N_SM9N_11 IO_L19P_SM9P_11 IO_L9N_CC_11 IO_L9P_CC_11 IO_L11N_CC_SM14N_11 IO_L11P_CC_SM14P_11 IO_L2N_15 IO_L2P_15 IO_L0N_15 IO_L0P_15 IO_L11N_CC_15 Top Con J7.002 J7.004 J7.006 J7.008 J7.010 J7.012 J7.014 J7.016 J7.018 J7.020 J7.022 J7.024 J7.026 J7.028 J7.030 J7.032 J7.034 J7.036 J7.038 J7.040 J7.042 J7.044 J7.046 J7.048 J7.050 Bottom Con JB7.002 JB7.004 JB7.006 JB7.008 JB7.010 JB7.012 JB7.014 JB7.016 JB7.018 JB7.020 JB7.022 JB7.024 JB7.026 JB7.028 JB7.030 JB7.032 JB7.034 JB7.036 JB7.038 JB7.040 JB7.042 JB7.044 JB7.046 JB7.048 JB7.050

J7 (Even Pins) FPGA IO Pin U2.G42 U2.F42 U2.K42 U2.J42 U2.M41 U2.L42 U2.N41 U2.M42 U2.P42 U2.R42 U2.U41 U2.T42 U2.V41 U2.U42 U2.Y42 U2.W42 U2.Y40 U2.W40 U2.Y38 U2.Y39 U2.E40 U2.E39 U2.G39 U2.G38 U2.J40 IO Description IO_L0N_11 IO_L0P_11 IO_L3N_11 IO_L3P_11 IO_L5N_11 IO_L5P_11 IO_L6N_11 IO_L6P_11 IO_L12N_VRP_11 IO_L12P_VRN_11 IO_L15N_SM13N_11 IO_L15P_SM13P_11 IO_L16N_SM12N_11 IO_L16P_SM12P_11 IO_L18N_SM10N_11 IO_L18P_SM10P_11 IO_L8N_CC_11 IO_L8P_CC_11 IO_L10N_CC_SM15N_11 IO_L10P_CC_SM15P_11 IO_L3N_15 IO_L3P_15 IO_L1N_15 IO_L1P_15 IO_L10N_CC_15

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

29

J7 (Odd Pins) Top Con J7.051 J7.053 J7.055 J7.057 J7.059 J7.061 J7.063 J7.065 J7.067 J7.069 J7.071 J7.073 J7.075 J7.077 J7.079 J7.081 J7.083 J7.085 J7.087 J7.089 J7.091 J7.093 J7.095 J7.097 J7.099 J7.101 J7.103 J7.105 J7.107 J7.109 J7.111 J7.113 J7.115 J7.117 J7.119 Bottom Con JB7.051 JB7.053 JB7.055 JB7.057 JB7.059 JB7.061 JB7.063 JB7.065 JB7.067 JB7.069 JB7.071 JB7.073 JB7.075 JB7.077 JB7.079 JB7.081 JB7.083 JB7.085 JB7.087 JB7.089 JB7.091 JB7.093 JB7.095 JB7.097 JB7.099 JB7.101 JB7.103 JB7.105 JB7.107 JB7.109 JB7.111 JB7.113 JB7.115 JB7.117 JB7.119 FPGA IO Pin U2.K40 U2.L39 U2.M38 U2.N38 U2.P38 U2.P37 U2.R37 U2.U38 U2.T37 U2.U37 U2.V38 U2.W35 U2.Y35 U2.Y34 U2.AA34 U2.AB38 U2.AB37 U2.AD40 U2.AE40 U2.AD42 U2.AC41 U2.AF42 U2.AF41 U2.AG41 U2.AF40 U2.AJ40 U2.AH40 U2.AL40 U2.AK40 U2.AN41 U2.AM41 U2.AT42 U2.AR42 U2.AU41 U2.AT41 IO Description IO_L11P_CC_15 IO_L8N_CC_15 IO_L8P_CC_15 IO_L6N_15 IO_L6P_15 IO_L5N_15 IO_L5P_15 IO_L13N_15 IO_L13P_15 IO_L12N_VRP_15 IO_L12P_VRN_15 IO_L18N_15 IO_L18P_15 IO_L17N_15 IO_L17P_15 IO_L8N_CC_SM1N_13 IO_L8P_CC_SM1P_13 IO_L10N_CC_13 IO_L10P_CC_13 IO_L1N_SM7N_13 IO_L1P_SM7P_13 IO_L3N_SM5N_13 IO_L3P_SM5P_13 IO_L4N_VREF_13 IO_L4P_13 IO_L7N_SM2N_13 IO_L7P_SM2P_13 IO_L12N_VRP_13 IO_L12P_VRN_13 IO_L15N_13 IO_L15P_13 IO_L17N_13 IO_L17P_13 IO_L18N_13 IO_L18P_13 Top Con J7.052 J7.054 J7.056 J7.058 J7.060 J7.062 J7.064 J7.066 J7.068 J7.070 J7.072 J7.074 J7.076 J7.078 J7.080 J7.082 J7.084 J7.086 J7.088 J7.090 J7.092 J7.094 J7.096 J7.098 J7.100 J7.102 J7.104 J7.106 J7.108 J7.110 J7.112 J7.114 J7.116 J7.118 J7.120 Bottom Con JB7.052 JB7.054 JB7.056 JB7.058 JB7.060 JB7.062 JB7.064 JB7.066 JB7.068 JB7.070 JB7.072 JB7.074 JB7.076 JB7.078 JB7.080 JB7.082 JB7.084 JB7.086 JB7.088 JB7.090 JB7.092 JB7.094 JB7.096 JB7.098 JB7.100 JB7.102 JB7.104 JB7.106 JB7.108 JB7.110 JB7.112 JB7.114 JB7.116 JB7.118 JB7.120

J7 (Even Pins) FPGA IO Pin U2.H40 U2.J38 U2.K38 U2.M39 U2.N39 U2.R38 U2.R39 U2.U39 U2.T39 U2.W38 U2.V39 U2.W37 U2.W36 U2.AA36 U2.AA35 U2.AC38 U2.AB39 U2.AC39 U2.AC40 U2.AB42 U2.AB41 U2.AD41 U2.AE42 U2.AH41 U2.AG42 U2.AJ41 U2.AJ42 U2.AK42 U2.AL41 U2.AM42 U2.AL42 U2.AP41 U2.AP42 U2.AV41 U2.AU42 IO Description IO_L10P_CC_15 IO_L9N_CC_15 IO_L9P_CC_15 IO_L7N_15 IO_L7P_15 IO_L4N_VREF_15 IO_L4P_15 IO_L14N_VREF_15 IO_L14P_15 IO_L15N_15 IO_L15P_15 IO_L19N_15 IO_L19P_15 IO_L16N_15 IO_L16P_15 IO_L9N_CC_SM0N_13 IO_L9P_CC_SM0P_13 IO_L11N_CC_13 IO_L11P_CC_13 IO_L0N_SM8N_13 IO_L0P_SM8P_13 IO_L2N_SM6N_13 IO_L2P_SM6P_13 IO_L5N_SM4N_13 IO_L5P_SM4P_13 IO_L6N_SM3N_13 IO_L6P_SM3P_13 IO_L13N_13 IO_L13P_13 IO_L14N_VREF_13 IO_L14P_13 IO_L16N_13 IO_L16P_13 IO_L19N_13 IO_L19P_13

J9 (Odd Pins) Top Con J9.001 J9.003 J9.005 J9.007 J9.009 J9.011 J9.013 J9.015 J9.017 J9.019 Bottom Con JB9.001 JB9.003 JB9.005 JB9.007 JB9.009 JB9.011 JB9.013 JB9.015 JB9.017 JB9.019 FPGA IO Pin U1.AJ11 U1.AJ10 U1.AL10 U1.AK10 U1.AM11 U1.AM12 U1.AN10 U1.AM9 U1.AP12 U1.AP11 IO Description IO_L18N_26 IO_L18P_26 IO_L17N_26 IO_L17P_26 IO_L15N_26 IO_L15P_26 IO_L13N_26 IO_L13P_26 IO_L11N_CC_26 IO_L11P_CC_26 Top Con J9.002 J9.004 J9.006 J9.008 J9.010 J9.012 J9.014 J9.016 J9.018 J9.020 Bottom Con JB9.002 JB9.004 JB9.006 JB9.008 JB9.010 JB9.012 JB9.014 JB9.016 JB9.018 JB9.020

J9 (Even Pins) FPGA IO Pin U1.AK12 U1.AJ12 U1.AL12 U1.AL11 U1.AP10 U1.AN11 U1.AP8 U1.AN9 U1.AT12 U1.AR12 IO Description IO_L19N_26 IO_L19P_26 IO_L16N_26 IO_L16P_26 IO_L14N_VREF_26 IO_L14P_26 IO_L12N_VRP_26 IO_L12P_VRN_26 IO_L10N_CC_26 IO_L10P_CC_26

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

30

J9 (Odd Pins) Top Con J9.021 J9.023 J9.025 J9.027 J9.029 J9.031 J9.033 J9.035 J9.037 J9.039 J9.041 J9.043 J9.045 J9.047 J9.049 J9.051 J9.053 J9.055 J9.057 J9.059 J9.061 J9.063 J9.065 J9.067 J9.069 J9.071 J9.073 J9.075 J9.077 J9.079 J9.081 J9.083 J9.085 J9.087 J9.089 J9.091 J9.093 J9.095 J9.097 J9.099 J9.101 J9.103 J9.105 J9.107 J9.109 J9.111 J9.113 J9.115 J9.117 J9.119 Bottom Con JB9.021 JB9.023 JB9.025 JB9.027 JB9.029 JB9.031 JB9.033 JB9.035 JB9.037 JB9.039 JB9.041 JB9.043 JB9.045 JB9.047 JB9.049 JB9.051 JB9.053 JB9.055 JB9.057 JB9.059 JB9.061 JB9.063 JB9.065 JB9.067 JB9.069 JB9.071 JB9.073 JB9.075 JB9.077 JB9.079 JB9.081 JB9.083 JB9.085 JB9.087 JB9.089 JB9.091 JB9.093 JB9.095 JB9.097 JB9.099 JB9.101 JB9.103 JB9.105 JB9.107 JB9.109 JB9.111 JB9.113 JB9.115 JB9.117 JB9.119 FPGA IO Pin U1.AU11 U1.AV11 U1.AR10 U1.AR9 U1.AT9 U1.AU9 U1.AR8 U1.AR7 U1.AU7 U1.AV6 U1.AF12 U1.AG12 U1.AE10 U1.AF11 U1.AF9 U1.AF10 U1.AG9 U1.AH10 U1.AG8 U1.AH8 U1.AK9 U1.AL9 U1.AM8 U1.AN8 U1.AP6 U1.AP7 U1.AT6 U1.AT5 U1.AV4 U1.AV5 U1.AC11 U1.AB11 U1.AB9 U1.AB8 U1.AB7 U1.AC8 U1.AE7 U1.AD6 U1.AF5 U1.AF6 U1.AH6 U1.AG6 U1.AG4 U1.AH4 U1.AL5 U1.AL6 U1.AN5 U1.AM6 U1.AN3 U1.AP3 IO Description IO_L7N_26 IO_L7P_26 IO_L9N_CC_26 IO_L9P_CC_26 IO_L4N_VREF_26 IO_L4P_26 IO_L3N_26 IO_L3P_26 IO_L0N_26 IO_L0P_26 IO_L8N_CC_22 IO_L8P_CC_22 IO_L0N_22 IO_L0P_22 IO_L2N_22 IO_L2P_22 IO_L7N_22 IO_L7P_22 IO_L4N_VREF_22 IO_L4P_22 IO_L11N_CC_22 IO_L11P_CC_22 IO_L13N_22 IO_L13P_22 IO_L15N_22 IO_L15P_22 IO_L18N_22 IO_L18P_22 IO_L16N_22 IO_L16P_22 IO_L0N_18 IO_L0P_18 IO_L3N_18 IO_L3P_18 IO_L4N_VREF_18 IO_L4P_18 IO_L6N_18 IO_L6P_18 IO_L9N_CC_18 IO_L9P_CC_18 IO_L10N_CC_18 IO_L10P_CC_18 IO_L11N_CC_18 IO_L11P_CC_18 IO_L14N_VREF_18 IO_L14P_18 IO_L19N_18 IO_L19P_18 IO_L16N_18 IO_L16P_18 Top Con J9.022 J9.024 J9.026 J9.028 J9.030 J9.032 J9.034 J9.036 J9.038 J9.040 J9.042 J9.044 J9.046 J9.048 J9.050 J9.052 J9.054 J9.056 J9.058 J9.060 J9.062 J9.064 J9.066 J9.068 J9.070 J9.072 J9.074 J9.076 J9.078 J9.080 J9.082 J9.084 J9.086 J9.088 J9.090 J9.092 J9.094 J9.096 J9.098 J9.100 J9.102 J9.104 J9.106 J9.108 J9.110 J9.112 J9.114 J9.116 J9.118 J9.120 Bottom Con JB9.022 JB9.024 JB9.026 JB9.028 JB9.030 JB9.032 JB9.034 JB9.036 JB9.038 JB9.040 JB9.042 JB9.044 JB9.046 JB9.048 JB9.050 JB9.052 JB9.054 JB9.056 JB9.058 JB9.060 JB9.062 JB9.064 JB9.066 JB9.068 JB9.070 JB9.072 JB9.074 JB9.076 JB9.078 JB9.080 JB9.082 JB9.084 JB9.086 JB9.088 JB9.090 JB9.092 JB9.094 JB9.096 JB9.098 JB9.100 JB9.102 JB9.104 JB9.106 JB9.108 JB9.110 JB9.112 JB9.114 JB9.116 JB9.118 JB9.120

J9 (Even Pins) FPGA IO Pin U1.AU12 U1.AU13 U1.AT11 U1.AT10 U1.AV9 U1.AV10 U1.AU6 U1.AT7 U1.AV8 U1.AU8 U1.AG11 U1.AH11 U1.AE8 U1.AE9 U1.AF7 U1.AG7 U1.AJ8 U1.AH9 U1.AK7 U1.AJ7 U1.AL7 U1.AK8 U1.AN6 U1.AM7 U1.AP5 U1.AR5 U1.AT4 U1.AU4 U1.AU3 U1.AV3 U1.AD10 U1.AD11 U1.AC9 U1.AC10 U1.AD8 U1.AD7 U1.AE5 U1.AD5 U1.AF4 U1.AE4 U1.AH5 U1.AJ6 U1.AK4 U1.AJ5 U1.AL4 U1.AK5 U1.AM4 U1.AN4 U1.AR4 U1.AR3 IO Description IO_L6N_26 IO_L6P_26 IO_L8N_CC_26 IO_L8P_CC_26 IO_L5N_26 IO_L5P_26 IO_L2N_26 IO_L2P_26 IO_L1N_26 IO_L1P_26 IO_L9N_CC_22 IO_L9P_CC_22 IO_L1N_22 IO_L1P_22 IO_L3N_22 IO_L3P_22 IO_L6N_22 IO_L6P_22 IO_L5N_22 IO_L5P_22 IO_L10N_CC_22 IO_L10P_CC_22 IO_L12N_VRP_22 IO_L12P_VRN_22 IO_L14N_VREF_22 IO_L14P_22 IO_L17N_22 IO_L17P_22 IO_L19N_22 IO_L19P_22 IO_L1N_18 IO_L1P_18 IO_L2N_18 IO_L2P_18 IO_L7N_18 IO_L7P_18 IO_L5N_18 IO_L5P_18 IO_L8N_CC_18 IO_L8P_CC_18 IO_L13N_18 IO_L13P_18 IO_L12N_VRP_18 IO_L12P_VRN_18 IO_L15N_18 IO_L15P_18 IO_L17N_18 IO_L17P_18 IO_L18N_18 IO_L18P_18

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

31

J10 (Odd Pins) Top Con J10.001 J10.003 J10.005 J10.007 J10.009 J10.011 J10.013 J10.015 J10.017 J10.019 J10.021 J10.023 J10.025 J10.027 J10.029 J10.031 J10.033 J10.035 J10.037 J10.039 J10.041 J10.043 J10.045 J10.047 J10.049 J10.051 J10.053 J10.055 J10.057 J10.059 J10.061 J10.063 J10.065 J10.067 J10.069 J10.071 J10.073 J10.075 J10.077 J10.079 J10.081 J10.083 J10.085 J10.087 J10.089 J10.091 J10.093 J10.095 J10.097 Bottom Con JB10.001 JB10.003 JB10.005 JB10.007 JB10.009 JB10.011 JB10.013 JB10.015 JB10.017 JB10.019 JB10.021 JB10.023 JB10.025 JB10.027 JB10.029 JB10.031 JB10.033 JB10.035 JB10.037 JB10.039 JB10.041 JB10.043 JB10.045 JB10.047 JB10.049 JB10.051 JB10.053 JB10.055 JB10.057 JB10.059 JB10.061 JB10.063 JB10.065 JB10.067 JB10.069 JB10.071 JB10.073 JB10.075 JB10.077 JB10.079 JB10.081 JB10.083 JB10.085 JB10.087 JB10.089 JB10.091 JB10.093 JB10.095 JB10.097 FPGA IO Pin U1.AT40 U1.AR40 U1.AP40 U1.AN40 U1.AM38 U1.AN38 U1.AL37 U1.AM37 U1.AK39 U1.AJ38 U1.AH38 U1.AJ37 U1.AF37 U1.AG37 U1.AD38 U1.AE37 U1.AD35 U1.AC36 U1.AB36 U1.AC35 U1.AU37 U1.AU38 U1.AT36 U1.AR37 U1.AN36 U1.AP35 U1.AM34 U1.AN34 U1.AK34 U1.AL34 U1.AK35 U1.AJ35 U1.AG34 U1.AH34 U1.AF34 U1.AF36 U1.AE32 U1.AD33 U1.AB32 U1.AB33 U1.AT35 U1.AU36 U1.AT34 U1.AU34 U1.AR34 U1.AR35 U1.AT31 U1.AT32 U1.AP32 IO Description IO_L9N_CC_17 IO_L9P_CC_17 IO_L8N_CC_17 IO_L8P_CC_17 IO_L18N_17 IO_L18P_17 IO_L19N_17 IO_L19P_17 IO_L13N_17 IO_L13P_17 IO_L15N_17 IO_L15P_17 IO_L7N_17 IO_L7P_17 IO_L4N_VREF_17 IO_L4P_17 IO_L2N_17 IO_L2P_17 IO_L1N_17 IO_L1P_17 IO_L5N_21 IO_L5P_21 IO_L7N_21 IO_L7P_21 IO_L13N_21 IO_L13P_21 IO_L15N_21 IO_L15P_21 IO_L19N_21 IO_L19P_21 IO_L17N_21 IO_L17P_21 IO_L10N_CC_21 IO_L10P_CC_21 IO_L8N_CC_21 IO_L9N_CC_21 IO_L2N_21 IO_L2P_21 IO_L0N_21 IO_L0P_21 IO_L5N_25 IO_L5P_25 IO_L6N_25 IO_L6P_25 IO_L7N_25 IO_L7P_25 IO_L11N_CC_25 IO_L11P_CC_25 IO_L13N_25 Top Con J10.002 J10.004 J10.006 J10.008 J10.010 J10.012 J10.014 J10.016 J10.018 J10.020 J10.022 J10.024 J10.026 J10.028 J10.030 J10.032 J10.034 J10.036 J10.038 J10.040 J10.042 J10.044 J10.046 J10.048 J10.050 J10.052 J10.054 J10.056 J10.058 J10.060 J10.062 J10.064 J10.066 J10.068 J10.070 J10.072 J10.074 J10.076 J10.078 J10.080 J10.082 J10.084 J10.086 J10.088 J10.090 J10.092 J10.094 J10.096 J10.098 Bottom Con JB10.002 JB10.004 JB10.006 JB10.008 JB10.010 JB10.012 JB10.014 JB10.016 JB10.018 JB10.020 JB10.022 JB10.024 JB10.026 JB10.028 JB10.030 JB10.032 JB10.034 JB10.036 JB10.038 JB10.040 JB10.042 JB10.044 JB10.046 JB10.048 JB10.050 JB10.052 JB10.054 JB10.056 JB10.058 JB10.060 JB10.062 JB10.064 JB10.066 JB10.068 JB10.070 JB10.072 JB10.074 JB10.076 JB10.078 JB10.080 JB10.082 JB10.084 JB10.086 JB10.088 JB10.090 JB10.092 JB10.094 JB10.096 JB10.098

J10 (Even Pins) FPGA IO Pin U1.AU39 U1.AV40 U1.AR39 U1.AT39 U1.AP38 U1.AN39 U1.AM39 U1.AL39 U1.AK37 U1.AK38 U1.AH39 U1.AG39 U1.AG38 U1.AF39 U1.AE38 U1.AE39 U1.AD37 U1.AD36 U1.AC34 U1.AB34 U1.AV38 U1.AV39 U1.AR38 U1.AT37 U1.AP36 U1.AP37 U1.AN35 U1.AM36 U1.AL35 U1.AL36 U1.AJ36 U1.AH36 U1.AG36 U1.AH35 U1.AE35 U1.AF35 U1.AE34 U1.AE33 U1.AD32 U1.AC33 U1.AV36 U1.AV35 U1.AV34 U1.AV33 U1.AU33 U1.AU32 U1.AU31 U1.AV31 U1.AP33 IO Description IO_L10N_CC_17 IO_L10P_CC_17 IO_L11N_CC_17 IO_L11P_CC_17 IO_L17N_17 IO_L17P_17 IO_L16N_17 IO_L16P_17 IO_L14N_VREF_17 IO_L14P_17 IO_L12N_VRP_17 IO_L12P_VRN_17 IO_L6N_17 IO_L6P_17 IO_L5N_17 IO_L5P_17 IO_L3N_17 IO_L3P_17 IO_L0N_17 IO_L0P_17 IO_L4N_VREF_21 IO_L4P_21 IO_L6N_21 IO_L6P_21 IO_L12N_VRP_21 IO_L12P_VRN_21 IO_L14N_VREF_21 IO_L14P_21 IO_L18N_21 IO_L18P_21 IO_L16N_21 IO_L16P_21 IO_L11N_CC_21 IO_L11P_CC_21 IO_L8P_CC_21 IO_L9P_CC_21 IO_L3N_21 IO_L3P_21 IO_L1N_21 IO_L1P_21 IO_L4N_VREF_25 IO_L4P_25 IO_L9N_CC_25 IO_L9P_CC_25 IO_L8N_CC_25 IO_L8P_CC_25 IO_L10N_CC_25 IO_L10P_CC_25 IO_L14N_VREF_25

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

32

J10 (Odd Pins) Top Con J10.099 J10.101 J10.103 J10.105 J10.107 J10.109 J10.111 J10.113 J10.115 J10.117 J10.119 Bottom Con JB10.099 JB10.101 JB10.103 JB10.105 JB10.107 JB10.109 JB10.111 JB10.113 JB10.115 JB10.117 JB10.119 FPGA IO Pin U1.AR32 U1.AN31 U1.AP31 U1.AM31 U1.AL31 U1.AK32 U1.AJ32 U1.AJ31 U1.AH31 U1.AF31 U1.AG31 IO Description IO_L13P_25 IO_L12N_VRP_25 IO_L12P_VRN_25 IO_L19N_25 IO_L19P_25 IO_L17N_25 IO_L17P_25 IO_L3N_25 IO_L3P_25 IO_L0N_25 IO_L0P_25 Top Con J10.100 J10.102 J10.104 J10.106 J10.108 J10.110 J10.112 J10.114 J10.116 J10.118 J10.120 Bottom Con JB10.100 JB10.102 JB10.104 JB10.106 JB10.108 JB10.110 JB10.112 JB10.114 JB10.116 JB10.118 JB10.120

J10 (Even Pins) FPGA IO Pin U1.AR33 U1.AM33 U1.AN33 U1.AM32 U1.AL32 U1.AJ33 U1.AK33 U1.AG32 U1.AH33 U1.AG33 U1.AF32 IO Description IO_L14P_25 IO_L15N_25 IO_L15P_25 IO_L18N_25 IO_L18P_25 IO_L16N_25 IO_L16P_25 IO_L2N_25 IO_L2P_25 IO_L1N_25 IO_L1P_25

J12 (Odd Pins) Top Con J12.001 J12.003 J12.005 J12.007 J12.009 J12.011 J12.013 J12.015 J12.017 J12.019 J12.021 J12.023 J12.025 J12.027 J12.029 J12.031 J12.033 J12.035 J12.037 J12.039 J12.041 J12.043 J12.045 J12.047 J12.049 J12.051 J12.053 J12.055 J12.057 J12.059 J12.061 J12.063 J12.065 J12.067 J12.069 Bottom Con JB12.001 JB12.003 JB12.005 JB12.007 JB12.009 JB12.011 JB12.013 JB12.015 JB12.017 JB12.019 JB12.021 JB12.023 JB12.025 JB12.027 JB12.029 JB12.031 JB12.033 JB12.035 JB12.037 JB12.039 JB12.041 JB12.043 JB12.045 JB12.047 JB12.049 JB12.051 JB12.053 JB12.055 JB12.057 JB12.059 JB12.061 JB12.063 JB12.065 JB12.067 JB12.069 FPGA IO Pin U1.G41 U1.F41 U1.J41 U1.H41 U1.L41 U1.L40 U1.P40 U1.N40 U1.R40 U1.P41 U1.T41 U1.T40 U1.W41 U1.V40 U1.AA41 U1.AA42 U1.AA39 U1.AA40 U1.AA37 U1.Y37 U1.F40 U1.F39 U1.H39 U1.H38 U1.K39 U1.K40 U1.L39 U1.M38 U1.N38 U1.P38 U1.P37 U1.R37 U1.U38 U1.T37 U1.U37 IO Description IO_L1N_11 IO_L1P_11 IO_L2N_11 IO_L2P_11 IO_L4N_VREF_11 IO_L4P_11 IO_L7N_11 IO_L7P_11 IO_L13N_11 IO_L13P_11 IO_L14N_VREF_11 IO_L14P_11 IO_L17N_SM11N_11 IO_L17P_SM11P_11 IO_L19N_SM9N_11 IO_L19P_SM9P_11 IO_L9N_CC_11 IO_L9P_CC_11 IO_L11N_CC_SM14N_11 IO_L11P_CC_SM14P_11 IO_L2N_15 IO_L2P_15 IO_L0N_15 IO_L0P_15 IO_L11N_CC_15 IO_L11P_CC_15 IO_L8N_CC_15 IO_L8P_CC_15 IO_L6N_15 IO_L6P_15 IO_L5N_15 IO_L5P_15 IO_L13N_15 IO_L13P_15 IO_L12N_VRP_15 Top Con J12.002 J12.004 J12.006 J12.008 J12.010 J12.012 J12.014 J12.016 J12.018 J12.020 J12.022 J12.024 J12.026 J12.028 J12.030 J12.032 J12.034 J12.036 J12.038 J12.040 J12.042 J12.044 J12.046 J12.048 J12.050 J12.052 J12.054 J12.056 J12.058 J12.060 J12.062 J12.064 J12.066 J12.068 J12.070 Bottom Con JB12.002 JB12.004 JB12.006 JB12.008 JB12.010 JB12.012 JB12.014 JB12.016 JB12.018 JB12.020 JB12.022 JB12.024 JB12.026 JB12.028 JB12.030 JB12.032 JB12.034 JB12.036 JB12.038 JB12.040 JB12.042 JB12.044 JB12.046 JB12.048 JB12.050 JB12.052 JB12.054 JB12.056 JB12.058 JB12.060 JB12.062 JB12.064 JB12.066 JB12.068 JB12.070

J12 (Even Pins) FPGA IO Pin U1.G42 U1.F42 U1.K42 U1.J42 U1.M41 U1.L42 U1.N41 U1.M42 U1.P42 U1.R42 U1.U41 U1.T42 U1.V41 U1.U42 U1.Y42 U1.W42 U1.Y40 U1.W40 U1.Y38 U1.Y39 U1.E40 U1.E39 U1.G39 U1.G38 U1.J40 U1.H40 U1.J38 U1.K38 U1.M39 U1.N39 U1.R38 U1.R39 U1.U39 U1.T39 U1.W38 IO Description IO_L0N_11 IO_L0P_11 IO_L3N_11 IO_L3P_11 IO_L5N_11 IO_L5P_11 IO_L6N_11 IO_L6P_11 IO_L12N_VRP_11 IO_L12P_VRN_11 IO_L15N_SM13N_11 IO_L15P_SM13P_11 IO_L16N_SM12N_11 IO_L16P_SM12P_11 IO_L18N_SM10N_11 IO_L18P_SM10P_11 IO_L8N_CC_11 IO_L8P_CC_11 IO_L10N_CC_SM15N_11 IO_L10P_CC_SM15P_11 IO_L3N_15 IO_L3P_15 IO_L1N_15 IO_L1P_15 IO_L10N_CC_15 IO_L10P_CC_15 IO_L9N_CC_15 IO_L9P_CC_15 IO_L7N_15 IO_L7P_15 IO_L4N_VREF_15 IO_L4P_15 IO_L14N_VREF_15 IO_L14P_15 IO_L15N_15

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

33

J12 (Odd Pins) Top Con J12.071 J12.073 J12.075 J12.077 J12.079 J12.081 J12.083 J12.085 J12.087 J12.089 J12.091 J12.093 J12.095 J12.097 J12.099 J12.101 J12.103 J12.105 J12.107 J12.109 J12.111 J12.113 J12.115 J12.117 J12.119 Bottom Con JB12.071 JB12.073 JB12.075 JB12.077 JB12.079 JB12.081 JB12.083 JB12.085 JB12.087 JB12.089 JB12.091 JB12.093 JB12.095 JB12.097 JB12.099 JB12.101 JB12.103 JB12.105 JB12.107 JB12.109 JB12.111 JB12.113 JB12.115 JB12.117 JB12.119 FPGA IO Pin U1.V38 U1.W35 U1.Y35 U1.Y34 U1.AA34 U1.AB38 U1.AB37 U1.AD40 U1.AE40 U1.AD42 U1.AC41 U1.AF42 U1.AF41 U1.AG41 U1.AF40 U1.AJ40 U1.AH40 U1.AL40 U1.AK40 U1.AN41 U1.AM41 U1.AT42 U1.AR42 U1.AU41 U1.AT41 IO Description IO_L12P_VRN_15 IO_L18N_15 IO_L18P_15 IO_L17N_15 IO_L17P_15 IO_L8N_CC_SM1N_13 IO_L8P_CC_SM1P_13 IO_L10N_CC_13 IO_L10P_CC_13 IO_L1N_SM7N_13 IO_L1P_SM7P_13 IO_L3N_SM5N_13 IO_L3P_SM5P_13 IO_L4N_VREF_13 IO_L4P_13 IO_L7N_SM2N_13 IO_L7P_SM2P_13 IO_L12N_VRP_13 IO_L12P_VRN_13 IO_L15N_13 IO_L15P_13 IO_L17N_13 IO_L17P_13 IO_L18N_13 IO_L18P_13 Top Con J12.072 J12.074 J12.076 J12.078 J12.080 J12.082 J12.084 J12.086 J12.088 J12.090 J12.092 J12.094 J12.096 J12.098 J12.100 J12.102 J12.104 J12.106 J12.108 J12.110 J12.112 J12.114 J12.116 J12.118 J12.120 Bottom Con JB12.072 JB12.074 JB12.076 JB12.078 JB12.080 JB12.082 JB12.084 JB12.086 JB12.088 JB12.090 JB12.092 JB12.094 JB12.096 JB12.098 JB12.100 JB12.102 JB12.104 JB12.106 JB12.108 JB12.110 JB12.112 JB12.114 JB12.116 JB12.118 JB12.120

J12 (Even Pins) FPGA IO Pin U1.V39 U1.W37 U1.W36 U1.AA36 U1.AA35 U1.AC38 U1.AB39 U1.AC39 U1.AC40 U1.AB42 U1.AB41 U1.AD41 U1.AE42 U1.AH41 U1.AG42 U1.AJ41 U1.AJ42 U1.AK42 U1.AL41 U1.AM42 U1.AL42 U1.AP41 U1.AP42 U1.AV41 U1.AU42 IO Description IO_L15P_15 IO_L19N_15 IO_L19P_15 IO_L16N_15 IO_L16P_15 IO_L9N_CC_SM0N_13 IO_L9P_CC_SM0P_13 IO_L11N_CC_13 IO_L11P_CC_13 IO_L0N_SM8N_13 IO_L0P_SM8P_13 IO_L2N_SM6N_13 IO_L2P_SM6P_13 IO_L5N_SM4N_13 IO_L5P_SM4P_13 IO_L6N_SM3N_13 IO_L6P_SM3P_13 IO_L13N_13 IO_L13P_13 IO_L14N_VREF_13 IO_L14P_13 IO_L16N_13 IO_L16P_13 IO_L19N_13 IO_L19P_13

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

34

8.1.4

Shared IO

Shared IO connectors are those labeled J1, J2, J5, J8, and J11, and are linked to the IO pins of both FPGAs U1 and U2. Should any shared IO be used as IO for one FPGA, take caution in assigning connections to avoid IO conflicts. The shared IO voltages are set at 3.3V and we do not recommend using LVDS or any other advanced Xilinx IO standard on the shared IO. In addition, the 12 shared IOs on J1 can also be used as external clocks or feedback lines, and therefore S2C recommends that these 12 lines be used as shared IO only as a secondary option. The shared IO connector properties are listed below: Table 8-5 Shared IO Connector Properties
J1 (Odd Pins) Top CON J1.001 J1.003 J1.005 J1.007 J1.009 J1.011 J1.013 J1.015 J1.017 J1.019 J1.021 J1.023 J1.025 J1.027 J1.029 J1.031 J1.033 J1.035 J1.037 J1.039 J1.041 J1.043 J1.045 J1.047 J1.049 J1.051 J1.053 J1.055 J1.057 J1.059 J1.061 J1.063 J1.065 J1.067 J1.069 J1.071 Bottom CON JB1.001 JB1.003 JB1.005 JB1.007 JB1.009 JB1.011 JB1.013 JB1.015 JB1.017 JB1.019 JB1.021 JB1.023 JB1.025 JB1.027 JB1.029 JB1.031 JB1.033 JB1.035 JB1.037 JB1.039 JB1.041 JB1.043 JB1.045 JB1.047 JB1.049 JB1.051 JB1.053 JB1.055 JB1.057 JB1.059 JB1.061 JB1.063 JB1.065 JB1.067 JB1.069 JB1.071 F1 Pin U1.E30 U1.D30 U1.F29 U1.F30 U1.E28 U1.E29 U1.D28 U1.D27 U1.E27 U1.F27 U1.F25 U1.F26 U1.D26 U1.D25 U1.E25 U1.E24 U1.F24 U1.E23 U1.D23 U1.D22 U1.H26 U1.G26 U1.J25 U1.H25 U1.G24 U1.H24 U1.G23 U1.H23 U1.F22 U1.G22 U1.H20 U1.G21 U1.G19 U1.H19 U1.G18 U1.G17 F2 Pin U2.E30 U2.D30 U2.F29 U2.F30 U2.E28 U2.E29 U2.D28 U2.D27 U2.E27 U2.F27 U2.F25 U2.F26 U2.D26 U2.D25 U2.E25 U2.E24 U2.F24 U2.E23 U2.D23 U2.D22 U2.H26 U2.G26 U2.J25 U2.H25 U2.G24 U2.H24 U2.G23 U2.H23 U2.F22 U2.G22 U2.H20 U2.G21 U2.G19 U2.H19 U2.G18 U2.G17 Top CON J1.002 J1.004 J1.006 J1.008 J1.010 J1.012 J1.014 J1.016 J1.018 J1.020 J1.022 J1.024 J1.026 J1.028 J1.030 J1.032 J1.034 J1.036 J1.038 J1.040 J1.042 J1.044 J1.046 J1.048 J1.050 J1.052 J1.054 J1.056 J1.058 J1.060 J1.062 J1.064 J1.066 J1.068 J1.070 J1.072 J1 (Even Pins) Bottom CON JB1.002 JB1.004 JB1.006 JB1.008 JB1.010 JB1.012 JB1.014 JB1.016 JB1.018 JB1.020 JB1.022 JB1.024 JB1.026 JB1.028 JB1.030 JB1.032 JB1.034 JB1.036 JB1.038 JB1.040 JB1.042 JB1.044 JB1.046 JB1.048 JB1.050 JB1.052 JB1.054 JB1.056 JB1.058 JB1.060 JB1.062 JB1.064 JB1.066 JB1.068 JB1.070 JB1.072 F1 Pin U1.E22 U1.F21 U1.D20 U1.D21 U1.F20 U1.E20 U1.F19 U1.E19 U1.E18 U1.D18 U1.E17 U1.F17 U1.D17 U1.D16 U1.F15 U1.F16 U1.F14 U1.E15 U1.D15 U1.E14 U1.D37 U1.E38 U1.E37 U1.F37 U1.G36 U1.F36 U1.G37 U1.H36 U1.J37 U1.K37 U1.J36 U1.H35 U1.J35 U1.K35 U1.L35 U1.L36 F2 Pin U2.E22 U2.F21 U2.D20 U2.D21 U2.F20 U2.E20 U2.F19 U2.E19 U2.E18 U2.D18 U2.E17 U2.F17 U2.D17 U2.D16 U2.F15 U2.F16 U2.F14 U2.E15 U2.D15 U2.E14 U2.D37 U2.E38 U2.E37 U2.F37 U2.G36 U2.F36 U2.G37 U2.H36 U2.J37 U2.K37 U2.J36 U2.H35 U2.J35 U2.K35 U2.L35 U2.L36

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

35

J1 (Odd Pins) Top CON J1.073 J1.075 J1.077 J1.079 J1.081 J1.083 J1.085 J1.087 J1.089 J1.091 J1.093 J1.095 J1.097 J1.099 J1.101 J1.103 J1.105 J1.107 J1.109 J1.111 J1.113 J1.115 J1.117 J1.119 Bottom CON JB1.073 JB1.075 JB1.077 JB1.079 JB1.081 JB1.083 JB1.085 JB1.087 JB1.089 JB1.091 JB1.093 JB1.095 JB1.097 JB1.099 JB1.101 JB1.103 JB1.105 JB1.107 JB1.109 JB1.111 JB1.113 JB1.115 JB1.117 JB1.119 F1 Pin U1.H18 U1.J18 U1.H21 U1.J21 U1.J23 U1.J22 U1.K23 U1.K22 U1.J20 U1.K20 U1.L21 U1.L20 U1.M22 U1.L22 U1.M21 U1.N22 U1.N23 U1.M23 U1.P22 U1.P23 U1.N21 U1.P21 U1.N20 U1.P20 F2 Pin U2.H18 U2.J18 U2.H21 U2.J21 U2.J23 U2.J22 U2.K23 U2.K22 U2.J20 U2.K20 U2.L21 U2.L20 U2.M22 U2.L22 U2.M21 U2.N22 U2.N23 U2.M23 U2.P22 U2.P23 U2.N21 U2.P21 U2.N20 U2.P20 Top CON J1.074 J1.076 J1.078 J1.080 J1.082 J1.084 J1.086 J1.088 J1.090 J1.092 J1.094 J1.096 J1.098 J1.100 J1.102 J1.104 J1.106 J1.108 J1.110 J1.112 J1.114 J1.116 J1.118 J1.120

J1 (Even Pins) Bottom CON JB1.074 JB1.076 JB1.078 JB1.080 JB1.082 JB1.084 JB1.086 JB1.088 JB1.090 JB1.092 JB1.094 JB1.096 JB1.098 JB1.100 JB1.102 JB1.104 JB1.106 JB1.108 JB1.110 JB1.112 JB1.114 JB1.116 JB1.118 JB1.120 F1 Pin U1.P36 U1.N36 U1.M37 U1.L37 U1.M36 U1.N35 U1.P35 U1.R34 U1.T36 U1.R35 U1.U33 U1.T34 U1.T35 U1.U34 U1.V36 U1.U36 U1.V34 U1.V35 U1.W33 U1.V33 U1.W32 U1.Y33 U1.AA32 U1.Y32 F2 Pin U2.P36 U2.N36 U2.M37 U2.L37 U2.M36 U2.N35 U2.P35 U2.R34 U2.T36 U2.R35 U2.U33 U2.T34 U2.T35 U2.U34 U2.V36 U2.U36 U2.V34 U2.V35 U2.W33 U2.V33 U2.W32 U2.Y33 U2.AA32 U2.Y32

J2 (Odd Pins) Top CON J2.001 J2.003 J2.005 J2.007 J2.009 J2.011 J2.013 J2.015 J2.017 J2.019 J2.021 J2.023 J2.025 J2.027 J2.029 J2.031 J2.033 J2.035 J2.037 Bottom CON JB2.001 JB2.003 JB2.005 JB2.007 JB2.009 JB2.011 JB2.013 JB2.015 JB2.017 JB2.019 JB2.021 JB2.023 JB2.025 JB2.027 JB2.029 JB2.031 JB2.033 JB2.035 JB2.037 F1 Pin U1.C41 U1.B42 U1.D41 U1.D40 U1.B38 U1.B39 U1.D38 U1.C38 U1.B36 U1.B37 U1.D36 U1.D35 U1.B34 U1.C34 U1.D33 U1.D32 U1.A31 U1.A30 U1.C31 F2 Pin U2.AL21 U2.AM21 U2.AJ20 U2.AJ21 U2.AN20 U2.AP20 U2.AT19 U2.AR20 U2.AR19 U2.AR18 U2.AJ18 U2.AK19 U2.AM19 U2.AL19 U2.AP18 U2.AN19 U2.AR17 U2.AP16 U2.AR14 Top CON J2.002 J2.004 J2.006 J2.008 J2.010 J2.012 J2.014 J2.016 J2.018 J2.020 J2.022 J2.024 J2.026 J2.028 J2.030 J2.032 J2.034 J2.036 J2.038

J2 (Even Pins) Bottom CON JB2.002 JB2.004 JB2.006 JB2.008 JB2.010 JB2.012 JB2.014 JB2.016 JB2.018 JB2.020 JB2.022 JB2.024 JB2.026 JB2.028 JB2.030 JB2.032 JB2.034 JB2.036 JB2.038 F1 Pin U1.B41 U1.A41 U1.D42 U1.E42 U1.A40 U1.A39 U1.C40 U1.C39 U1.A36 U1.A37 U1.C35 U1.C36 U1.A35 U1.A34 U1.C33 U1.B33 U1.B32 U1.A32 U1.C30 F2 Pin U2.AM22 U2.AL22 U2.AL20 U2.AK20 U2.AP21 U2.AN21 U2.AT21 U2.AT20 U2.AT17 U2.AT16 U2.AL17 U2.AK18 U2.AM17 U2.AM18 U2.AP17 U2.AN18 U2.AP15 U2.AR15 U2.AT15

J2.039

JB2.039

U1.D31

U2.AR13

J2.040

JB2.040

U1.B31

U2.AT14

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

36

J2 (Odd Pins) Top CON J2.041 J2.043 J2.045 J2.047 J2.049 J2.051 J2.053 J2.055 J2.057 J2.059 J2.061 J2.063 J2.065 J2.067 J2.069 J2.071 J2.073 J2.075 J2.077 J2.079 J2.081 J2.083 J2.085 J2.087 J2.089 J2.091 J2.093 J2.095 J2.097 J2.099 J2.101 J2.103 J2.105 J2.107 J2.109 J2.111 J2.113 J2.115 J2.117 J2.119 Bottom CON JB2.041 JB2.043 JB2.045 JB2.047 JB2.049 JB2.051 JB2.053 JB2.055 JB2.057 JB2.059 JB2.061 JB2.063 JB2.065 JB2.067 JB2.069 JB2.071 JB2.073 JB2.075 JB2.077 JB2.079 JB2.081 JB2.083 JB2.085 JB2.087 JB2.089 JB2.091 JB2.093 JB2.095 JB2.097 JB2.099 JB2.101 JB2.103 JB2.105 JB2.107 JB2.109 JB2.111 JB2.113 JB2.115 JB2.117 JB2.119 F1 Pin U1.C28 U1.C29 U1.A26 U1.B27 U1.C25 U1.C24 U1.A24 U1.B23 U1.B22 U1.C23 U1.C20 U1.C21 U1.C19 U1.C18 U1.B18 U1.B17 U1.C15 U1.C14 U1.B14 U1.B13 U1.C11 U1.B11 U1.D12 U1.D11 U1.D10 U1.C10 U1.D8 U1.C9 U1.C6 U1.B6 U1.D6 U1.D7 U1.D5 U1.C5 U1.C4 U1.D3 U1.B1 U1.C1 U1.D2 U1.D1 F2 Pin U2.AV20 U2.AV21 U2.AY20 U2.BA20 U2.AU19 U2.AU18 U2.BA19 U2.AY19 U2.AU16 U2.AU17 U2.AY18 U2.AY17 U2.AV16 U2.AW16 U2.BA16 U2.BB16 U2.AV14 U2.AU14 U2.AY15 U2.AY14 U2.AW12 U2.AW11 U2.BB12 U2.BA12 U2.AW10 U2.AY10 U2.AY9 U2.AY8 U2.AW8 U2.AY7 U2.AW6 U2.AW7 U2.AW5 U2.AY5 U2.BA4 U2.AY4 U2.AW3 U2.AY3 U2.AY2 U2.AW2 Top CON J2.042 J2.044 J2.046 J2.048 J2.050 J2.052 J2.054 J2.056 J2.058 J2.060 J2.062 J2.064 J2.066 J2.068 J2.070 J2.072 J2.074 J2.076 J2.078 J2.080 J2.082 J2.084 J2.086 J2.088 J2.090 J2.092 J2.094 J2.096 J2.098 J2.100 J2.102 J2.104 J2.106 J2.108 J2.110 J2.112 J2.114 J2.116 J2.118 J2.120

J2 (Even Pins) Bottom CON JB2.042 JB2.044 JB2.046 JB2.048 JB2.050 JB2.052 JB2.054 JB2.056 JB2.058 JB2.060 JB2.062 JB2.064 JB2.066 JB2.068 JB2.070 JB2.072 JB2.074 JB2.076 JB2.078 JB2.080 JB2.082 JB2.084 JB2.086 JB2.088 JB2.090 JB2.092 JB2.094 JB2.096 JB2.098 JB2.100 JB2.102 JB2.104 JB2.106 JB2.108 JB2.110 JB2.112 JB2.114 JB2.116 JB2.118 JB2.120 F1 Pin U1.B29 U1.A29 U1.A27 U1.B28 U1.B26 U1.C26 U1.A25 U1.B24 U1.A22 U1.A21 U1.B21 U1.A20 U1.B19 U1.A19 U1.A17 U1.A16 U1.C16 U1.B16 U1.A15 U1.A14 U1.A12 U1.B12 U1.D13 U1.C13 U1.A10 U1.A11 U1.B9 U1.A9 U1.B7 U1.A7 U1.B8 U1.C8 U1.A6 U1.A5 U1.A4 U1.B4 U1.B2 U1.A2 U1.C3 U1.B3 F2 Pin U2.AW20 U2.AW21 U2.BB22 U2.BB21 U2.AV19 U2.AW18 U2.BB19 U2.BB18 U2.AV18 U2.AW17 U2.BA17 U2.BB17 U2.AV15 U2.AW15 U2.BB14 U2.BA15 U2.AW13 U2.AV13 U2.BA14 U2.BB13 U2.AY12 U2.AY13 U2.BA11 U2.BB11 U2.BA10 U2.BB9 U2.BA9 U2.BB8 U2.BA7 U2.BB7 U2.BA6 U2.BB6 U2.BB4 U2.BA5 U2.BB3 U2.BB2 U2.BA2 U2.BA1 U2.AW1 U2.AV1

J5 (Odd Pins) Top CON J5.001 J5.003 J5.005 Bottom CON JB5.001 JB5.003 JB5.005 F1 Pin U1.AU1 U1.AU2 U1.AP2 F2 Pin U2.AW40 U2.AW41 U2.BA41 Top CON J5.002 J5.004 J5.006

J5 (Even Pins) Bottom CON JB5.002 JB5.004 JB5.006 F1 Pin U1.AT2 U1.AT1 U1.AN1 F2 Pin U2.AW42 U2.AY42 U2.BB41

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

37

J5 (Odd Pins) Top CON J5.007 J5.009 J5.011 J5.013 J5.015 J5.017 J5.019 J5.021 J5.023 J5.025 J5.027 J5.029 J5.031 J5.033 J5.035 J5.037 J5.039 J5.041 J5.043 J5.045 J5.047 J5.049 J5.051 J5.053 J5.055 J5.057 J5.059 J5.061 J5.063 J5.065 J5.067 J5.069 J5.071 J5.073 J5.075 J5.077 J5.079 J5.081 J5.083 J5.085 J5.087 J5.089 J5.091 J5.093 J5.095 J5.097 J5.099 J5.101 Bottom CON JB5.007 JB5.009 JB5.011 JB5.013 JB5.015 JB5.017 JB5.019 JB5.021 JB5.023 JB5.025 JB5.027 JB5.029 JB5.031 JB5.033 JB5.035 JB5.037 JB5.039 JB5.041 JB5.043 JB5.045 JB5.047 JB5.049 JB5.051 JB5.053 JB5.055 JB5.057 JB5.059 JB5.061 JB5.063 JB5.065 JB5.067 JB5.069 JB5.071 JB5.073 JB5.075 JB5.077 JB5.079 JB5.081 JB5.083 JB5.085 JB5.087 JB5.089 JB5.091 JB5.093 JB5.095 JB5.097 JB5.099 JB5.101 F1 Pin U1.AR2 U1.AM2 U1.AM3 U1.AK3 U1.AL2 U1.AJ3 U1.AJ2 U1.AH3 U1.AG3 U1.AE3 U1.AD2 U1.AD1 U1.AC1 U1.AD3 U1.AC3 U1.AC6 U1.AB6 U1.AA10 U1.AA11 U1.Y9 U1.Y10 U1.AA6 U1.AA7 U1.W8 U1.W7 U1.V5 U1.U6 U1.T5 U1.T6 U1.P5 U1.N5 U1.L4 U1.L5 U1.J3 U1.H4 U1.F4 U1.G4 U1.AA5 U1.Y5 U1.Y3 U1.Y2 U1.W3 U1.W2 U1.V4 U1.V3 U1.T2 U1.R2 U1.R3 F2 Pin U2.AY40 U2.BA39 U2.BB38 U2.AW37 U2.AY38 U2.AW36 U2.AY37 U2.AW35 U2.AY35 U2.BA34 U2.BB33 U2.AW32 U2.AW33 U2.BA32 U2.AY32 U2.AW31 U2.AY30 U2.AY29 U2.BA29 U2.AW28 U2.AV29 U2.AY28 U2.AY27 U2.AU27 U2.AU28 U2.BA25 U2.BB24 U2.AU26 U2.AV26 U2.AY24 U2.AY25 U2.AU24 U2.AV25 U2.AY23 U2.AY22 U2.AU22 U2.AU23 U2.AR30 U2.AT30 U2.AP27 U2.AP28 U2.AN25 U2.AN26 U2.AM24 U2.AL25 U2.AK24 U2.AJ25 U2.AT24 Top CON J5.008 J5.010 J5.012 J5.014 J5.016 J5.018 J5.020 J5.022 J5.024 J5.026 J5.028 J5.030 J5.032 J5.034 J5.036 J5.038 J5.040 J5.042 J5.044 J5.046 J5.048 J5.050 J5.052 J5.054 J5.056 J5.058 J5.060 J5.062 J5.064 J5.066 J5.068 J5.070 J5.072 J5.074 J5.076 J5.078 J5.080 J5.082 J5.084 J5.086 J5.088 J5.090 J5.092 J5.094 J5.096 J5.098 J5.100 J5.102

J5 (Even Pins) Bottom CON JB5.008 JB5.010 JB5.012 JB5.014 JB5.016 JB5.018 JB5.020 JB5.022 JB5.024 JB5.026 JB5.028 JB5.030 JB5.032 JB5.034 JB5.036 JB5.038 JB5.040 JB5.042 JB5.044 JB5.046 JB5.048 JB5.050 JB5.052 JB5.054 JB5.056 JB5.058 JB5.060 JB5.062 JB5.064 JB5.066 JB5.068 JB5.070 JB5.072 JB5.074 JB5.076 JB5.078 JB5.080 JB5.082 JB5.084 JB5.086 JB5.088 JB5.090 JB5.092 JB5.094 JB5.096 JB5.098 JB5.100 JB5.102 F1 Pin U1.AP1 U1.AL1 U1.AM1 U1.AJ1 U1.AK2 U1.AG1 U1.AH1 U1.AG2 U1.AF2 U1.AF1 U1.AE2 U1.AB1 U1.AB2 U1.AB4 U1.AB3 U1.AC5 U1.AC4 U1.W10 U1.W11 U1.AA9 U1.Y8 U1.W6 U1.Y7 U1.V6 U1.W5 U1.T4 U1.U4 U1.R4 U1.R5 U1.M4 U1.N4 U1.K4 U1.K3 U1.G3 U1.H3 U1.E4 U1.E3 U1.Y4 U1.AA4 U1.AA2 U1.AA1 U1.V1 U1.W1 U1.U2 U1.U3 U1.T1 U1.U1 U1.P1 F2 Pin U2.BA42 U2.BB39 U2.BA40 U2.AY39 U2.AW38 U2.BA37 U2.BB37 U2.BA36 U2.BB36 U2.BA35 U2.BB34 U2.AY34 U2.AY33 U2.BB31 U2.BB32 U2.BA31 U2.BA30 U2.BB28 U2.BB29 U2.AW30 U2.AV30 U2.BB27 U2.BA27 U2.AV28 U2.AW27 U2.BA26 U2.BB26 U2.AW25 U2.AW26 U2.BA24 U2.BB23 U2.AV23 U2.AV24 U2.BA22 U2.BA21 U2.AW22 U2.AW23 U2.AT29 U2.AU29 U2.AR29 U2.AR28 U2.AR27 U2.AP26 U2.AM26 U2.AL26 U2.AK25 U2.AL24 U2.AT26

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

38

J5 (Odd Pins) Top CON J5.103 J5.105 J5.107 J5.109 J5.111 J5.113 J5.115 J5.117 J5.119 Bottom CON JB5.103 JB5.105 JB5.107 JB5.109 JB5.111 JB5.113 JB5.115 JB5.117 JB5.119 F1 Pin U1.P3 U1.N3 U1.M3 U1.M2 U1.L2 U1.J1 U1.J2 U1.F2 U1.E2 F2 Pin U2.AT25 U2.AR24 U2.AR23 U2.AN23 U2.AM23 U2.AP22 U2.AR22 U2.AJ22 U2.AJ23 Top CON J5.104 J5.106 J5.108 J5.110 J5.112 J5.114 J5.116 J5.118 J5.120

J5 (Even Pins) Bottom CON JB5.104 JB5.106 JB5.108 JB5.110 JB5.112 JB5.114 JB5.116 JB5.118 JB5.120 F1 Pin U1.P2 U1.N1 U1.M1 U1.L1 U1.K2 U1.H1 U1.G1 U1.F1 U1.G2 F2 Pin U2.AT27 U2.AR25 U2.AP25 U2.AN24 U2.AP23 U2.AT22 U2.AU21 U2.AK22 U2.AK23

J8 (Odd Pins) Top CON J8.001 J8.003 J8.005 J8.007 J8.009 J8.011 J8.013 J8.015 J8.017 J8.019 J8.021 J8.023 J8.025 J8.027 J8.029 J8.031 J8.033 J8.035 J8.037 J8.039 J8.041 J8.043 J8.045 J8.047 J8.049 J8.051 J8.053 J8.055 J8.057 J8.059 J8.061 J8.063 J8.065 J8.067 Bottom CON JB8.001 JB8.003 JB8.005 JB8.007 JB8.009 JB8.011 JB8.013 JB8.015 JB8.017 JB8.019 JB8.021 JB8.023 JB8.025 JB8.027 JB8.029 JB8.031 JB8.033 JB8.035 JB8.037 JB8.039 JB8.041 JB8.043 JB8.045 JB8.047 JB8.049 JB8.051 JB8.053 JB8.055 JB8.057 JB8.059 JB8.061 JB8.063 JB8.065 JB8.067 F1 Pin U1.AL21 U1.AM21 U1.AJ20 U1.AJ21 U1.AN20 U1.AP20 U1.AT19 U1.AR20 U1.AR19 U1.AR18 U1.AJ18 U1.AK19 U1.AM19 U1.AL19 U1.AP18 U1.AN19 U1.AR17 U1.AP16 U1.AR14 U1.AR13 U1.AV20 U1.AV21 U1.AY20 U1.BA20 U1.AU19 U1.AU18 U1.BA19 U1.AY19 U1.AU16 U1.AU17 U1.AY18 U1.AY17 U1.AV16 U1.AW16 F2 Pin U2.C41 U2.B42 U2.D41 U2.D40 U2.B38 U2.B39 U2.D38 U2.C38 U2.B36 U2.B37 U2.D36 U2.D35 U2.B34 U2.C34 U2.D33 U2.D32 U2.A31 U2.A30 U2.C31 U2.D31 U2.C28 U2.C29 U2.A26 U2.B27 U2.C25 U2.C24 U2.A24 U2.B23 U2.B22 U2.C23 U2.C20 U2.C21 U2.C19 U2.C18 Top CON J8.002 J8.004 J8.006 J8.008 J8.010 J8.012 J8.014 J8.016 J8.018 J8.020 J8.022 J8.024 J8.026 J8.028 J8.030 J8.032 J8.034 J8.036 J8.038 J8.040 J8.042 J8.044 J8.046 J8.048 J8.050 J8.052 J8.054 J8.056 J8.058 J8.060 J8.062 J8.064 J8.066 J8.068

J8 (Even Pins) Bottom CON JB8.002 JB8.004 JB8.006 JB8.008 JB8.010 JB8.012 JB8.014 JB8.016 JB8.018 JB8.020 JB8.022 JB8.024 JB8.026 JB8.028 JB8.030 JB8.032 JB8.034 JB8.036 JB8.038 JB8.040 JB8.042 JB8.044 JB8.046 JB8.048 JB8.050 JB8.052 JB8.054 JB8.056 JB8.058 JB8.060 JB8.062 JB8.064 JB8.066 JB8.068 F1 Pin U1.AM22 U1.AL22 U1.AL20 U1.AK20 U1.AP21 U1.AN21 U1.AT21 U1.AT20 U1.AT17 U1.AT16 U1.AL17 U1.AK18 U1.AM17 U1.AM18 U1.AP17 U1.AN18 U1.AP15 U1.AR15 U1.AT15 U1.AT14 U1.AW20 U1.AW21 U1.BB22 U1.BB21 U1.AV19 U1.AW18 U1.BB19 U1.BB18 U1.AV18 U1.AW17 U1.BA17 U1.BB17 U1.AV15 U1.AW15 F2 Pin U2.B41 U2.A41 U2.D42 U2.E42 U2.A40 U2.A39 U2.C40 U2.C39 U2.A36 U2.A37 U2.C35 U2.C36 U2.A35 U2.A34 U2.C33 U2.B33 U2.B32 U2.A32 U2.C30 U2.B31 U2.B29 U2.A29 U2.A27 U2.B28 U2.B26 U2.C26 U2.A25 U2.B24 U2.A22 U2.A21 U2.B21 U2.A20 U2.B19 U2.A19

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

39

J8 (Odd Pins) Top CON J8.069 J8.071 J8.073 J8.075 J8.077 J8.079 J8.081 J8.083 J8.085 J8.087 J8.089 J8.091 J8.093 J8.095 J8.097 J8.099 J8.101 J8.103 J8.105 J8.107 J8.109 J8.111 J8.113 J8.115 J8.117 J8.119 Bottom CON JB8.069 JB8.071 JB8.073 JB8.075 JB8.077 JB8.079 JB8.081 JB8.083 JB8.085 JB8.087 JB8.089 JB8.091 JB8.093 JB8.095 JB8.097 JB8.099 JB8.101 JB8.103 JB8.105 JB8.107 JB8.109 JB8.111 JB8.113 JB8.115 JB8.117 JB8.119 F1 Pin U1.BA16 U1.BB16 U1.AV14 U1.AU14 U1.AY15 U1.AY14 U1.AW12 U1.AW11 U1.BB12 U1.BA12 U1.AW10 U1.AY10 U1.AY9 U1.AY8 U1.AW8 U1.AY7 U1.AW6 U1.AW7 U1.AW5 U1.AY5 U1.BA4 U1.AY4 U1.AW3 U1.AY3 U1.AY2 U1.AW2 F2 Pin U2.B18 U2.B17 U2.C15 U2.C14 U2.B14 U2.B13 U2.C11 U2.B11 U2.D12 U2.D11 U2.D10 U2.C10 U2.D8 U2.C9 U2.C6 U2.B6 U2.D6 U2.D7 U2.D5 U2.C5 U2.C4 U2.D3 U2.B1 U2.C1 U2.D2 U2.D1 Top CON J8.070 J8.072 J8.074 J8.076 J8.078 J8.080 J8.082 J8.084 J8.086 J8.088 J8.090 J8.092 J8.094 J8.096 J8.098 J8.100 J8.102 J8.104 J8.106 J8.108 J8.110 J8.112 J8.114 J8.116 J8.118 J8.120

J8 (Even Pins) Bottom CON JB8.070 JB8.072 JB8.074 JB8.076 JB8.078 JB8.080 JB8.082 JB8.084 JB8.086 JB8.088 JB8.090 JB8.092 JB8.094 JB8.096 JB8.098 JB8.100 JB8.102 JB8.104 JB8.106 JB8.108 JB8.110 JB8.112 JB8.114 JB8.116 JB8.118 JB8.120 F1 Pin U1.BB14 U1.BA15 U1.AW13 U1.AV13 U1.BA14 U1.BB13 U1.AY12 U1.AY13 U1.BA11 U1.BB11 U1.BA10 U1.BB9 U1.BA9 U1.BB8 U1.BA7 U1.BB7 U1.BA6 U1.BB6 U1.BB4 U1.BA5 U1.BB3 U1.BB2 U1.BA2 U1.BA1 U1.AW1 U1.AV1 F2 Pin U2.A17 U2.A16 U2.C16 U2.B16 U2.A15 U2.A14 U2.A12 U2.B12 U2.D13 U2.C13 U2.A10 U2.A11 U2.B9 U2.A9 U2.B7 U2.A7 U2.B8 U2.C8 U2.A6 U2.A5 U2.A4 U2.B4 U2.B2 U2.A2 U2.C3 U2.B3

J11 (Odd Pins) Top CON J11.001 J11.003 J11.005 J11.007 J11.009 J11.011 J11.013 J11.015 J11.017 J11.019 J11.021 J11.023 J11.025 J11.027 J11.029 J11.031 J11.033 Bottom CON JB11.001 JB11.003 JB11.005 JB11.007 JB11.009 JB11.011 JB11.013 JB11.015 JB11.017 JB11.019 JB11.021 JB11.023 JB11.025 JB11.027 JB11.029 JB11.031 JB11.033 F1 Pin U1.AW40 U1.AW41 U1.BA41 U1.AY40 U1.BA39 U1.BB38 U1.AW37 U1.AY38 U1.AW36 U1.AY37 U1.AW35 U1.AY35 U1.BA34 U1.BB33 U1.AW32 U1.AW33 U1.BA32 F2 Pin U2.AU1 U2.AU2 U2.AP2 U2.AR2 U2.AM2 U2.AM3 U2.AK3 U2.AL2 U2.AJ3 U2.AJ2 U2.AH3 U2.AG3 U2.AE3 U2.AD2 U2.AD1 U2.AC1 U2.AD3 Top CON J11.002 J11.004 J11.006 J11.008 J11.010 J11.012 J11.014 J11.016 J11.018 J11.020 J11.022 J11.024 J11.026 J11.028 J11.030 J11.032 J11.034

J11 (Even Pins) Bottom CON JB11.002 JB11.004 JB11.006 JB11.008 JB11.010 JB11.012 JB11.014 JB11.016 JB11.018 JB11.020 JB11.022 JB11.024 JB11.026 JB11.028 JB11.030 JB11.032 JB11.034 F1 Pin U1.AW42 U1.AY42 U1.BB41 U1.BA42 U1.BB39 U1.BA40 U1.AY39 U1.AW38 U1.BA37 U1.BB37 U1.BA36 U1.BB36 U1.BA35 U1.BB34 U1.AY34 U1.AY33 U1.BB31 F2 Pin U2.AT2 U2.AT1 U2.AN1 U2.AP1 U2.AL1 U2.AM1 U2.AJ1 U2.AK2 U2.AG1 U2.AH1 U2.AG2 U2.AF2 U2.AF1 U2.AE2 U2.AB1 U2.AB2 U2.AB4

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

40

J11 (Odd Pins) Top CON J11.035 J11.037 J11.039 J11.041 J11.043 J11.045 J11.047 J11.049 J11.051 J11.053 J11.055 J11.057 J11.059 J11.061 J11.063 J11.065 J11.067 J11.069 J11.071 J11.073 J11.075 J11.077 J11.079 J11.081 J11.083 J11.085 J11.087 J11.089 J11.091 J11.093 J11.095 J11.097 J11.099 J11.101 J11.103 J11.105 J11.107 J11.109 J11.111 J11.113 J11.115 J11.117 J11.119 Bottom CON JB11.035 JB11.037 JB11.039 JB11.041 JB11.043 JB11.045 JB11.047 JB11.049 JB11.051 JB11.053 JB11.055 JB11.057 JB11.059 JB11.061 JB11.063 JB11.065 JB11.067 JB11.069 JB11.071 JB11.073 JB11.075 JB11.077 JB11.079 JB11.081 JB11.083 JB11.085 JB11.087 JB11.089 JB11.091 JB11.093 JB11.095 JB11.097 JB11.099 JB11.101 JB11.103 JB11.105 JB11.107 JB11.109 JB11.111 JB11.113 JB11.115 JB11.117 JB11.119 F1 Pin U1.AY32 U1.AW31 U1.AY30 U1.AY29 U1.BA29 U1.AW28 U1.AV29 U1.AY28 U1.AY27 U1.AU27 U1.AU28 U1.BA25 U1.BB24 U1.AU26 U1.AV26 U1.AY24 U1.AY25 U1.AU24 U1.AV25 U1.AY23 U1.AY22 U1.AU22 U1.AU23 U1.AR30 U1.AT30 U1.AP27 U1.AP28 U1.AN25 U1.AN26 U1.AM24 U1.AL25 U1.AK24 U1.AJ25 U1.AT24 U1.AT25 U1.AR24 U1.AR23 U1.AN23 U1.AM23 U1.AP22 U1.AR22 U1.AJ22 U1.AJ23 F2 Pin U2.AC3 U2.AC6 U2.AB6 U2.AA10 U2.AA11 U2.Y9 U2.Y10 U2.AA6 U2.AA7 U2.W8 U2.W7 U2.V5 U2.U6 U2.T5 U2.T6 U2.P5 U2.N5 U2.L4 U2.L5 U2.J3 U2.H4 U2.F4 U2.G4 U2.AA5 U2.Y5 U2.Y3 U2.Y2 U2.W3 U2.W2 U2.V4 U2.V3 U2.T2 U2.R2 U2.R3 U2.P3 U2.N3 U2.M3 U2.M2 U2.L2 U2.J1 U2.J2 U2.F2 U2.E2 Top CON J11.036 J11.038 J11.040 J11.042 J11.044 J11.046 J11.048 J11.050 J11.052 J11.054 J11.056 J11.058 J11.060 J11.062 J11.064 J11.066 J11.068 J11.070 J11.072 J11.074 J11.076 J11.078 J11.080 J11.082 J11.084 J11.086 J11.088 J11.090 J11.092 J11.094 J11.096 J11.098 J11.100 J11.102 J11.104 J11.106 J11.108 J11.110 J11.112 J11.114 J11.116 J11.118 J11.120

J11 (Even Pins) Bottom CON JB11.036 JB11.038 JB11.040 JB11.042 JB11.044 JB11.046 JB11.048 JB11.050 JB11.052 JB11.054 JB11.056 JB11.058 JB11.060 JB11.062 JB11.064 JB11.066 JB11.068 JB11.070 JB11.072 JB11.074 JB11.076 JB11.078 JB11.080 JB11.082 JB11.084 JB11.086 JB11.088 JB11.090 JB11.092 JB11.094 JB11.096 JB11.098 JB11.100 JB11.102 JB11.104 JB11.106 JB11.108 JB11.110 JB11.112 JB11.114 JB11.116 JB11.118 JB11.120 F1 Pin U1.BB32 U1.BA31 U1.BA30 U1.BB28 U1.BB29 U1.AW30 U1.AV30 U1.BB27 U1.BA27 U1.AV28 U1.AW27 U1.BA26 U1.BB26 U1.AW25 U1.AW26 U1.BA24 U1.BB23 U1.AV23 U1.AV24 U1.BA22 U1.BA21 U1.AW22 U1.AW23 U1.AT29 U1.AU29 U1.AR29 U1.AR28 U1.AR27 U1.AP26 U1.AM26 U1.AL26 U1.AK25 U1.AL24 U1.AT26 U1.AT27 U1.AR25 U1.AP25 U1.AN24 U1.AP23 U1.AT22 U1.AU21 U1.AK22 U1.AK23 F2 Pin U2.AB3 U2.AC5 U2.AC4 U2.W10 U2.W11 U2.AA9 U2.Y8 U2.W6 U2.Y7 U2.V6 U2.W5 U2.T4 U2.U4 U2.R4 U2.R5 U2.M4 U2.N4 U2.K4 U2.K3 U2.G3 U2.H3 U2.E4 U2.E3 U2.Y4 U2.AA4 U2.AA2 U2.AA1 U2.V1 U2.W1 U2.U2 U2.U3 U2.T1 U2.U1 U2.P1 U2.P2 U2.N1 U2.M1 U2.L1 U2.K2 U2.H1 U2.G1 U2.F1 U2.G2

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

41

8.1.5

SODIMM IO

The SODIMM IO connectors are used to plug in DDR2 memory modules to the SODIMM sockets. Pin connections and functions support different Xilinx IO standards as described in Table 8-5. Table 8-6
Net Name A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 BA0 BA1 BA2 CAS_B CKE0 CKE1 CLKN0 CLKN1 CLKP0 CLKP1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQ0 DQ1 DQ10 DQ11 DQ12 DQ13

SODIMM Dedicated Pin Properties
SODIMM Pin U_SODIMM1.102 U_SODIMM1.101 U_SODIMM1.100 U_SODIMM1.99 U_SODIMM1.98 U_SODIMM1.97 U_SODIMM1.94 U_SODIMM1.92 U_SODIMM1.93 U_SODIMM1.91 U_SODIMM1.105 U_SODIMM1.90 U_SODIMM1.89 U_SODIMM1.116 U_SODIMM1.107 U_SODIMM1.106 U_SODIMM1.85 U_SODIMM1.113 U_SODIMM1.79 U_SODIMM1.80 U_SODIMM1.32 U_SODIMM1.166 U_SODIMM1.30 U_SODIMM1.164 U_SODIMM1.10 U_SODIMM1.26 U_SODIMM1.52 U_SODIMM1.67 U_SODIMM1.130 U_SODIMM1.147 U_SODIMM1.170 U_SODIMM1.185 U_SODIMM1.5 U_SODIMM1.7 U_SODIMM1.35 U_SODIMM1.37 U_SODIMM1.20 U_SODIMM1.22 FPGA IO Pin U1.M24 U1.N24 U1.L25 U1.L24 U1.M26 U1.L26 U1.P27 U1.R28 U1.P26 U1.R27 U1.N19 U1.N28 U1.P28 U1.P15 U1.N18 U1.P18 U1.N29 U1.R15 U1.U31 U1.T31 U1.N25 U1.L19 U1.P25 U1.K19 U1.H34 U1.K32 U1.T32 U1.K25 U1.M17 U1.P12 U1.E10 U1.L9 U1.N34 U1.N33 U1.M31 U1.M32 U1.J33 U1.K33 IO Description IO_L0P_5 IO_L0N_5 IO_L2P_5 IO_L2N_5 IO_L6P_5 IO_L6N_5 IO_L2P_A15_D31_1 IO_L0P_A19_1 IO_L2N_A14_D30_1 IO_L0N_A18_1 IO_L16N_5 IO_L4P_A11_D27_1 IO_L4N_VREF_A10_D26_1 IO_L5N_A8_D24_1 IO_L16P_5 IO_L18N_5 IO_L6P_A7_D23_1 IO_L9N_CC_A0_D16_1 IO_L19P_23 IO_L19N_23 IO_L8N_CC_5 IO_L9N_CC_5 IO_L8P_CC_5 IO_L9P_CC_5 IO_L4P_23 IO_L14P_23 IO_L18P_23 IO_L4P_5 IO_L14P_5 IO_L0P_24 IO_L14P_24 IO_L4P_24 IO_L0N_23 IO_L0P_23 IO_L2N_23 IO_L2P_23 IO_L14N_VREF_23 IO_L13P_23

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

42

Net Name DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ2 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ3 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ4 DQ40 DQ41 DQ42 DQ43 DQ441 DQ45 DQ46 DQ47 DQ48 DQ49 DQ5 DQ50 DQ51 DQ52 DQ53

SODIMM Pin U_SODIMM1.36 U_SODIMM1.38 U_SODIMM1.43 U_SODIMM1.45 U_SODIMM1.55 U_SODIMM1.57 U_SODIMM1.17 U_SODIMM1.44 U_SODIMM1.46 U_SODIMM1.56 U_SODIMM1.58 U_SODIMM1.61 U_SODIMM1.63 U_SODIMM1.73 U_SODIMM1.75 U_SODIMM1.62 U_SODIMM1.64 U_SODIMM1.19 U_SODIMM1.74 U_SODIMM1.76 U_SODIMM1.123 U_SODIMM1.125 U_SODIMM1.135 U_SODIMM1.137 U_SODIMM1.124 U_SODIMM1.126 U_SODIMM1.134 U_SODIMM1.136 U_SODIMM1.4 U_SODIMM1.141 U_SODIMM1.143 U_SODIMM1.151 U_SODIMM1.153 U_SODIMM1.140 U_SODIMM1.142 U_SODIMM1.152 U_SODIMM1.154 U_SODIMM1.157 U_SODIMM1.159 U_SODIMM1.6 U_SODIMM1.173 U_SODIMM1.175 U_SODIMM1.158 U_SODIMM1.160

FPGA IO Pin U1.J31 U1.H31 U1.P32 U1.P33 U1.R32 U1.R33 U1.M33 U1.E33 U1.E32 U1.L31 U1.L32 U1.H30 U1.H29 U1.K27 U1.J28 U1.G29 U1.G28 U1.M34 U1.H28 U1.G27 U1.J16 U1.J17 U1.J15 U1.H15 U1.G16 U1.H16 U1.H14 U1.G14 U1.H33 U1.M11 U1.N11 U1.N10 U1.P10 U1.J12 U1.K12 U1.J11 U1.J10 U1.L12 U1.M12 U1.G33 U1.L10 U1.L11 U1.H10 U1.H9

IO Description IO_L7N_23 IO_L7P_23 IO_L16N_23 IO_L16P_23 IO_L17N_23 IO_L17P_23 IO_L1N_23 IO_L11N_CC_23 IO_L11P_CC_23 IO_L15N_23 IO_L15P_23 IO_L19N_5 IO_L19P_5 IO_L13N_5 IO_L13P_5 IO_L17N_5 IO_L17P_5 IO_L1P_23 IO_L15N_5 IO_L15P_5 IO_L5N_5 IO_L5P_5 IO_L7N_5 IO_L7P_5 IO_L3N_5 IO_L3P_5 IO_L1N_5 IO_L1P_5 IO_L5N_23 IO_L3N_24 IO_L3P_24 IO_L1N_24 IO_L1P_24 IO_L6N_24 IO_L6P_24 IO_L7N_24 IO_L7P_24 IO_L2N_24 IO_L2P_24 IO_L5P_23 IO_L5N_24 IO_L5P_24 IO_L13N_24 IO_L13P_24

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

43

Net Name DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ6 DQ60 DQ61 DQ62 DQ63 DQ7 DQ8 DQ9 DQSN0 DQSN1 DQSN2 DQSN3 DQSN4 DQSN5 DQSN6 DQSN7 DQSP0 DQSP1 DQSP2 DQSP3 DQSP4 DQSP5 DQSP6 DQSP7 NC/S1 ODT0 ODT1 RAS_B S0_B SA0 SA1 SCL SDA WE_B

SODIMM Pin U_SODIMM1.174 U_SODIMM1.176 U_SODIMM1.179 U_SODIMM1.181 U_SODIMM1.189 U_SODIMM1.191 U_SODIMM1.14 U_SODIMM1.180 U_SODIMM1.182 U_SODIMM1.192 U_SODIMM1.194 U_SODIMM1.16 U_SODIMM1.23 U_SODIMM1.25 U_SODIMM1.11 U_SODIMM1.29 U_SODIMM1.49 U_SODIMM1.68 U_SODIMM1.129 U_SODIMM1.146 U_SODIMM1.167 U_SODIMM1.186 U_SODIMM1.13 U_SODIMM1.31 U_SODIMM1.51 U_SODIMM1.70 U_SODIMM1.131 U_SODIMM1.148 U_SODIMM1.169 U_SODIMM1.188 U_SODIMM1.115 U_SODIMM1.114 U_SODIMM1.119 U_SODIMM1.108 U_SODIMM1.110 U_SODIMM1.198 U_SODIMM1.200 U_SODIMM1.197 U_SODIMM1.195 U_SODIMM1.109

FPGA IO Pin U1.G9 U1.F9 U1.K9 U1.K8 U1.J8 U1.H8 U1.G31 U1.G8 U1.F7 U1.E8 U1.E7 U1.G32 U1.P31 U1.N31 U1.E35 U1.F34 U1.F32 U1.J27 U1.M19 U1.E13 U1.G12 U1.G11 U1.F35 U1.E34 U1.F31 U1.J26 U1.M18 U1.E12 U1.H11 U1.F12 U1.P16 U1.N15 U1.P13 U1.R18 U1.R17 U1.H13 U1.G13 U1.N13 U1.M13 U1.P17

IO Description IO_L15N_24 IO_L15P_24 IO_L17N_24 IO_L17P_24 IO_L16N_24 IO_L16P_24 IO_L6N_23 IO_L19N_24 IO_L19P_24 IO_L18N_24 IO_L18P_24 IO_L6P_23 IO_L3N_23 IO_L3P_23 IO_L8N_CC_23 IO_L9N_CC_23 IO_L10N_CC_23 IO_L11N_CC_5 IO_L10N_CC_5 IO_L10N_CC_24 IO_L9N_CC_24 IO_L11N_CC_24 IO_L8P_CC_23 IO_L9P_CC_23 IO_L10P_CC_23 IO_L11P_CC_5 IO_L10P_CC_5 IO_L10P_CC_24 IO_L9P_CC_24 IO_L11P_CC_24 IO_L9P_CC_A1_D17_1 IO_L5P_A9_D25_1 IO_L7N_A4_D20_1 IO_L18P_5 IO_L3N_A12_D28_1 IO_L8P_CC_24 IO_L8N_CC_24 IO_L1N_A16_1 IO_L1P_A17_1 IO_L3P_A13_D29_1

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

44

Table 8-7
Net Name A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 BA0 BA1 BA2 CAS_B CKE0 CKE1 CLKN0 CLKN1 CLKP0 CLKP1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQ0 DQ1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19

SODIMM2 Dedicated Pin Properties
SODIMM Pin U_SODIMM2.102 U_SODIMM2.101 U_SODIMM2.100 U_SODIMM2.99 U_SODIMM2.98 U_SODIMM2.97 U_SODIMM2.94 U_SODIMM2.92 U_SODIMM2.93 U_SODIMM2.91 U_SODIMM2.105 U_SODIMM2.90 U_SODIMM2.89 U_SODIMM2.116 U_SODIMM2.107 U_SODIMM2.106 U_SODIMM2.85 U_SODIMM2.113 U_SODIMM2.79 U_SODIMM2.80 U_SODIMM2.32 U_SODIMM2.166 U_SODIMM2.30 U_SODIMM2.164 U_SODIMM2.10 U_SODIMM2.26 U_SODIMM2.52 U_SODIMM2.67 U_SODIMM2.130 U_SODIMM2.147 U_SODIMM2.170 U_SODIMM2.185 U_SODIMM2.5 U_SODIMM2.7 U_SODIMM2.35 U_SODIMM2.37 U_SODIMM2.20 U_SODIMM2.22 U_SODIMM2.36 U_SODIMM2.38 U_SODIMM2.43 U_SODIMM2.45 U_SODIMM2.55 U_SODIMM2.57 FPGA IO Pin U2.M24 U2.N24 U2.L25 U2.L24 U2.M26 U2.L26 U2.P27 U2.R28 U2.P26 U2.R27 U2.N19 U2.N28 U2.P28 U2.P15 U2.N18 U2.P18 U2.N29 U2.R15 U2.U31 U2.T31 U2.N25 U2.L19 U2.P25 U2.K19 U2.H34 U2.K32 U2.T32 U2.K25 U2.M17 U2.P12 U2.E10 U2.L9 U2.N34 U2.N33 U2.M31 U2.M32 U2.J33 U2.K33 U2.J31 U2.H31 U2.P32 U2.P33 U2.R32 U2.R33 IO Description IO_L0P_5 IO_L0N_5 IO_L2P_5 IO_L2N_5 IO_L6P_5 IO_L6N_5 IO_L2P_A15_D31_1 IO_L0P_A19_1 IO_L2N_A14_D30_1 IO_L0N_A18_1 IO_L16N_5 IO_L4P_A11_D27_1 IO_L4N_VREF_A10_D26_1 IO_L5N_A8_D24_1 IO_L16P_5 IO_L18N_5 IO_L6P_A7_D23_1 IO_L9N_CC_A0_D16_1 IO_L19P_23 IO_L19N_23 IO_L8N_CC_5 IO_L9N_CC_5 IO_L8P_CC_5 IO_L9P_CC_5 IO_L4P_23 IO_L14P_23 IO_L18P_23 IO_L4P_5 IO_L14P_5 IO_L0P_24 IO_L14P_24 IO_L4P_24 IO_L0N_23 IO_L0P_23 IO_L2N_23 IO_L2P_23 IO_L14N_VREF_23 IO_L13P_23 IO_L7N_23 IO_L7P_23 IO_L16N_23 IO_L16P_23 IO_L17N_23 IO_L17P_23

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

45

Net Name DQ2 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ3 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ4 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ5 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ6

SODIMM Pin U_SODIMM2.17 U_SODIMM2.44 U_SODIMM2.46 U_SODIMM2.56 U_SODIMM2.58 U_SODIMM2.61 U_SODIMM2.63 U_SODIMM2.73 U_SODIMM2.75 U_SODIMM2.62 U_SODIMM2.64 U_SODIMM2.19 U_SODIMM2.74 U_SODIMM2.76 U_SODIMM2.123 U_SODIMM2.125 U_SODIMM2.135 U_SODIMM2.137 U_SODIMM2.124 U_SODIMM2.126 U_SODIMM2.134 U_SODIMM2.136 U_SODIMM2.4 U_SODIMM2.141 U_SODIMM2.143 U_SODIMM2.151 U_SODIMM2.153 U_SODIMM2.140 U_SODIMM2.142 U_SODIMM2.152 U_SODIMM2.154 U_SODIMM2.157 U_SODIMM2.159 U_SODIMM2.6 U_SODIMM2.173 U_SODIMM2.175 U_SODIMM2.158 U_SODIMM2.160 U_SODIMM2.174 U_SODIMM2.176 U_SODIMM2.179 U_SODIMM2.181 U_SODIMM2.189 U_SODIMM2.191 U_SODIMM2.14

FPGA IO Pin U2.M33 U2.E33 U2.E32 U2.L31 U2.L32 U2.H30 U2.H29 U2.K27 U2.J28 U2.G29 U2.G28 U2.M34 U2.H28 U2.G27 U2.J16 U2.J17 U2.J15 U2.H15 U2.G16 U2.H16 U2.H14 U2.G14 U2.H33 U2.M11 U2.N11 U2.N10 U2.P10 U2.J12 U2.K12 U2.J11 U2.J10 U2.L12 U2.M12 U2.G33 U2.L10 U2.L11 U2.H10 U2.H9 U2.G9 U2.F9 U2.K9 U2.K8 U2.J8 U2.H8 U2.G31

IO Description IO_L1N_23 IO_L11N_CC_23 IO_L11P_CC_23 IO_L15N_23 IO_L15P_23 IO_L19N_5 IO_L19P_5 IO_L13N_5 IO_L13P_5 IO_L17N_5 IO_L17P_5 IO_L1P_23 IO_L15N_5 IO_L15P_5 IO_L5N_5 IO_L5P_5 IO_L7N_5 IO_L7P_5 IO_L3N_5 IO_L3P_5 IO_L1N_5 IO_L1P_5 IO_L5N_23 IO_L3N_24 IO_L3P_24 IO_L1N_24 IO_L1P_24 IO_L6N_24 IO_L6P_24 IO_L7N_24 IO_L7P_24 IO_L2N_24 IO_L2P_24 IO_L5P_23 IO_L5N_24 IO_L5P_24 IO_L13N_24 IO_L13P_24 IO_L15N_24 IO_L15P_24 IO_L17N_24 IO_L17P_24 IO_L16N_24 IO_L16P_24 IO_L6N_23

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

46

Net Name DQ60 DQ61 DQ62 DQ63 DQ7 DQ8 DQ9 DQSN0 DQSN1 DQSN2 DQSN3 DQSN4 DQSN5 DQSN6 DQSN7 DQSP0 DQSP1 DQSP2 DQSP3 DQSP4 DQSP5 DQSP6 DQSP7 NC/S1 ODT0 ODT1 RAS_B S0_B SA0 SA1 SCL SDA WE_B

SODIMM Pin U_SODIMM2.180 U_SODIMM2.182 U_SODIMM2.192 U_SODIMM2.194 U_SODIMM2.16 U_SODIMM2.23 U_SODIMM2.25 U_SODIMM2.11 U_SODIMM2.29 U_SODIMM2.49 U_SODIMM2.68 U_SODIMM2.129 U_SODIMM2.146 U_SODIMM2.167 U_SODIMM2.186 U_SODIMM2.13 U_SODIMM2.31 U_SODIMM2.51 U_SODIMM2.70 U_SODIMM2.131 U_SODIMM2.148 U_SODIMM2.169 U_SODIMM2.188 U_SODIMM2.115 U_SODIMM2.114 U_SODIMM2.119 U_SODIMM2.108 U_SODIMM2.110 U_SODIMM2.198 U_SODIMM2.200 U_SODIMM2.197 U_SODIMM2.195 U_SODIMM2.109

FPGA IO Pin U2.G8 U2.F7 U2.E8 U2.E7 U2.G32 U2.P31 U2.N31 U2.E35 U2.F34 U2.F32 U2.J27 U2.M19 U2.E13 U2.G12 U2.G11 U2.F35 U2.E34 U2.F31 U2.J26 U2.M18 U2.E12 U2.H11 U2.F12 U2.P16 U2.N15 U2.P13 U2.R18 U2.R17 U2.H13 U2.G13 U2.N13 U2.M13 U2.P17

IO Description IO_L19N_24 IO_L19P_24 IO_L18N_24 IO_L18P_24 IO_L6P_23 IO_L3N_23 IO_L3P_23 IO_L8N_CC_23 IO_L9N_CC_23 IO_L10N_CC_23 IO_L11N_CC_5 IO_L10N_CC_5 IO_L10N_CC_24 IO_L9N_CC_24 IO_L11N_CC_24 IO_L8P_CC_23 IO_L9P_CC_23 IO_L10P_CC_23 IO_L11P_CC_5 IO_L10P_CC_5 IO_L10P_CC_24 IO_L9P_CC_24 IO_L11P_CC_24 IO_L9P_CC_A1_D17_1 IO_L5P_A9_D25_1 IO_L7N_A4_D20_1 IO_L18P_5 IO_L3N_A12_D28_1 IO_L8P_CC_24 IO_L8N_CC_24 IO_L1N_A16_1 IO_L1P_A17_1 IO_L3P_A13_D29_1

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

47

9. Mating Connectors and Cables
This section provides information on TAI Logic Module-compatible connectors and cables. You can either directly purchase these parts from the vendor or contact S2C sales on how to order them.

9.1.1

EXT Clock SMB

You can input six global clocks using standard SMB connectors and cables.

9.1.2

External IO (JX & JBX Connectors)

TAI Logic Module uses Samtec’s Micro High Speed Interfaces - Q Strip series of sockets and terminals for external IO. These connectors allow you to connect TAI Logic Module to other hardware in three ways: (i) directly mount a target board onto TAI Logic Module, (ii) connect a target board and TAI Logic Module by cable, and (iii) stack multiple TAI Logic Modules together. Figure 9-1 Board Connection Methods

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

48

All IO connectors (including both dedicated and shared IO connectors) keep the same relative spacing between each other. If your target board requires mounting on multiple IO connectors, the spatial relationship among the connectors is as follows: Figure 9-2 TAI Logic Module JX Connector Spacing

The specifications of the components needed to mate the external IO connectors are as follows: Top side (Terminal connector; use socket connector to mate) Manufacturer: Part Number: Mates With: Samtec QTH-060-01-F-D-A QSH QSH-EM

Bottom side (Socket connector; use terminal connector or cable to mate) Manufacturer: Part Number: Mates With: Samtec QSH-060-01-F-D-A QTH QTH-EM HQCD HQDP HFHM2-SE

You can also mate the socket with Samtec’s HQCD-060-12.00-SEU-SED-1 cable interface as detailed below.

Manufacturer: Part Number: Mates With: More Info:

Samtec HQCD-060-12.00-SEU-SED-1 (Samtec 120-way Cable) QSH QTH QTH-DP QTH-EM QSH-DP QSH-EM

http://www.samtec.com/signal_integrity/technical_specifications/overview.asp? series=HQCD

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

49

10. Care and Handling
Please take the following safety precautions in the care and handling of your TAI Logic Module:

10.1.1 Safety Precautions
TAI Logic Module contains sensitive FPGA components. Make sure that you work in an anti-static environment and take all necessary anti-static handling precautions before unpacking and operating TAI Logic Module. For details, refer to section 9.1.2. All FPGA IO pins are directly drawn out to optimize application flexibility and performance, and thus do NOT have any protection. As such, any voltage above 3.3V or logic shortcut may lead to permanent FPGA IO pin damage. Do not connect TAI Logic Module’s IOs to any target device with a voltage above 3.3V. Also make sure that all IO connectors are securely connected before powering on. When probing TAI Logic Module IOs with a logic analyzer or oscilloscope, make sure that the probing tool does not touch adjacent pins, which may cause a short circuit, and that the test equipment has the same ground as TAI Logic Module does. Ensure that TAI Logic Module and the target systems share the same stable ground. Unstable ground may cause a design malfunction and damage either TAI Logic Module or your target systems. None of the IO connectors are hot plug-and-play. First power off TAI Logic Module before removing or inserting cables or daughter boards onto it. Follow proper power on and off sequences to reduce the risk of damaging TAI Logic Module’s FPGA pins. We highly recommend that you first power on TAI Logic Module before powering on the target systems that are connected to it. Conversely, when powering off your system, first power off your target systems before powering off TAI Logic Module. TAI Logic Module supports only 12V DC power supplies, through the power adapter socket. Inputting any voltage above 12V will damage your TAI Logic Module. Pressure and/or shaking may damage TAI Logic Module. High temperatures, high voltages, moisture, dust, static, and magnetization should also be avoided. TAI Logic Module should not be cleaned with or come into contact with any liquids.

10.1.2 Electrostatic Handling Considerations
TAI Logic Module is packaged in antistatic or conductive containers. Before taking it out of its container, make sure the module is in a static-free workstation (location). TAI Logic Module must remain in its protective packaging unless it is being used in a static-free location. Transport the module only in its original container to avoid any potential damage to the pins. Before removing TAI Logic Module from its packaging, place the package on a grounded bench top, ensure a wrist strap is snugly worn around your wrist and is properly plugged into the ground receptacle, and then ground your hands by placing them in contact with the conductive bench top.
Dual Virtex-5 TAI Logic Module Reference Manual v1.11

50

A conductive shoe strap with conductive tiles or mats may be used instead of the wrist strap. Once you leave the workstation, you must still follow the previous procedures when you return to work with the module at the static-free location. Do not place TAI Logic Module in contact with plastic snow polystyrene foam, styrofoam peanuts, or other high-dielectric materials, unless these materials have been treated with an antistatic agent (treated materials appear pink and generate less than 100V). Do not transport TAI Logic Module or store it in trays, tote boxes, vials, or other containers made of untreated plastic, unless it is protected within its original packaging.

NOTE: Please save the original packaging for future shipment needs.

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

51

11. Glossary
Term Co-emulation Definition A method of verification that links simulators to FPGA prototypes and ASIC emulators through the use of PLI, FLI, etc. A methodology that combines various models (i.e. behavior, FPGA-based, RTL, and silicon) through the use of BFM and C-API to generate a virtual prototype. Electronic System Level. A methodology using high level abstraction models (higher than RTL) to create and verify SoC designs. A prototype of an SoC or ASIC using FPGAs. An ESL environment using FPGA-based IP models. IP represented in the FPGA format. System-On-Chip. A single chip that functions as a whole system, which combines at least one processor (such as an embedded CPU or DSP), digital or analog IP, memory, and responding firmware and software. Small Outline Dual Inline Memory Module. A DIMM module with a thinner profile due to the use of TSOP chip packages. FPGA-based hardware certified by S2C as having the ability to configure and debug TAI IP modules to build SoC prototypes. TAI IP is an encrypted representation of any IP in FPGA netlist format with TAI structure insertions. High-level abstraction packets such as CPU instruction and network packets.

Co-modeling

ESL FPGA Prototype FPGA-based ESL FPGA-based IP SoC SODIMM TAI-compliant Hardware

TAI IP Transaction

For more terms related to the S2C methodology, please visit: http://www.s2cinc.com/methodology/glossary.htm.

Dual Virtex-5 TAI Logic Module Reference Manual v1.11

52


相关文档

brocade300 Hardware Reference Manual
VME-6015 Hardware Reference Manual
SingleA Virtex-7 TAI LM Hardware Reference Manual - V051914
ELVIS Hardware User Manual
DS-16B2 HARDWARE REFERENCE MANUAL
GTS-4E_Hardware_Integration_Manual_V1.0.0
Trio翠欧MC4X Hardware Reference Manual V7.5
CX600 - Hardware Reference
电脑版