# 1.8-MHz, 48-V resonant vrm analysis, design, and performance evaluation_图文

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 1, JANUARY 2006

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1.8-MHz, 48-V Resonant VRM: Analysis, Design, and Performance Evaluation

? Laszlo Huber, Member, IEEE, Kevin Hsu, Milan M. Jovanovic, Fellow, IEEE, Dennis J. Solley, Gennady Gurov, and Robert M. Porter

Abstract—A detailed analysis of operation and a basic design procedure for a new high-frequency (HF) resonant-converter technology with phase-shifted regulation is presented. The new HF resonant technology has a good potential to be a cost-effective solution for the voltage regulation modules (VRMs) for the next generations of microprocessor systems. The new HF resonant technology is employed in the development of a 1.8-MHz, 48-V, 130-W (0.95–1.7 V, 100 A) VRM. Experimental results are provided. Index Terms—High-frequency (HF), phase-shifted regulations, resonant converter, voltage regulation modules (VRMs).

I. INTRODUCTION

T

O FURTHER increase the processing speed and ef?ciency, future generations of microprocessor systems require lower operating voltages (below 1 V) at higher load currents (above 130 A) with high slew rates (up to 150 A s) [1]. High load currents with high slew rates and tighter output-voltage regulation windows require voltage regulation modules (VRMs) with fast transient responses. To achieve a fast transient response, the power conversion must be performed at higher switching frequencies (above 1 MHz). Higher switching frequencies enable controls with higher bandwidth feedback, which in turn require less output capacitance. As a result, only surface mount ceramic capacitors can be used at the output, which are less expensive and potentially more reliable than the commonly used electrolytic and tantalum capacitors. Further, at increased power levels, the 48-V distribution bus voltage is more feasible than the 12-V distribution bus voltage in order to keep the distribution losses low, especially for the high-end server and workstation applications [2]. To meet all these requirements, new high-performance VRM topologies and control technologies are needed. Recently, a new high-frequency (HF) resonant-converter technology with phase-shifted regulation was introduced in [3] and [4]. This HF resonant technology has proven to be a cost-effective solution for VRMs for the next generation of microprocessor systems. To facilitate the understanding of the new resonant technology, in this paper a detailed analysis of operation and a basic design procedure for the new HF resonant converter

Fig. 1. Simpli?ed circuit diagram of the new resonant converter [3], [4].

with phase-shifted regulation are presented. The new HF resonant-converter technology with phase-shifted regulation is employed in the development of a 1.8-MHz, 48-V, 130-W (0.95–1.7 V, 100 A) resonant VRM. The paper is organized as follows. In Section II, a detailed analysis of operation is performed. In Section III, a basic design procedure is given. The implementation of the 1.8-MHz, 48-V, 130-W resonant VRM is presented in Section IV. Experimental results are provided in Section V. II. ANALYSIS A. Principle of Operation The simpli?ed circuit diagram of the new resonant converter with phase-shifted regulation is shown in Fig. 1. This is an isolated converter with a half-bridge inverter on the primary side and a current-doubler recti?er on the secondary side. The primary-side half-bridge inverter operates in open loop with 50% duty cycle and generates a rectangular (trapezoidal) ac voltage. The secondary-side current-doubler recti?er uses synchronous recti?ers and . Diodes and represent the body diodes of the synchronous recti?ers. For the resonant operation, an external inductor is added in series with the transformer primary winding, and capacitors and are added in parallel to the synchronous recti?ers. To simplify the analysis, it is assumed that output-?lter inductances and and output-?lter capacitance are suf?ciently large, so that they can be represented with current sources 2 and a voltage source , respectively, as shown in the equivalent circuit in Fig. 2. Also, it is assumed that synchronous recti?ers and are ideal, except for their output

Manuscript received May 17, 2004; revised March 10, 2005. Recommended by Associate Editor J. Cobos. ? L. Huber and M. M. Jovanovic are with the Power Electronics Laboratory, Delta Products Corporation, Research Triangle Park, NC 27709, USA (e-mail: lhuber@deltartp.com). K. Hsu is with Delta Electronics, Inc., Taoyuan Shien, Taiwan, R.O.C. D. J. Solley, G. Gurov, and R. M. Porter are with Advanced Energy Industries, Inc., Fort Collins, CO 80525 USA. Digital Object Identi?er 10.1109/TPEL.2005.861203

0885-8993/$20.00 ? 2006 IEEE

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Fig. 2.

Equivalent circuit of the new resonant converter.

Fig. 3. Simpli?ed equivalent circuit of the new resonant converter.

capacitances, which are included into the parallel resonant caand . Finally, it is assumed that the magnepacitances tizing inductance of transformer is suf?ciently large, so that it can be neglected, while the leakage inductance of the trans. The total priformer is lumped with external inductance mary-side inductance is denoted as resonant inductance , as shown in Fig. 2. For simplicity, in Fig. 2, the primary-side halfbridge inverter in Fig 1. is replaced by a rectangular ac voltage . To further simplify the analysis, transformer source in Fig. 2 is eliminated by transferring the whole primary-side circuit to the secondary side, as shown in Fig. 3. In Fig. 3, the from the primary side to the secondary side is transferred denoted as , while the transferred ac voltage source is denoted as . Under steady-state operation, six topological stages can be , as shown in Fig. 4. identi?ed within a switching cycle These six topological stages can be arranged in two modes of operation. In the ?rst mode of operation, the sequence of topoa , while logical stages is a in the second mode of operation the sequence of topological stages is a f . Key waveforms in the two modes of operation are presented in Figs. 5 and 6. In Mode I, shown in Fig. 5, the resonant voltage on capacitors and reaches zero before ac voltage changes direction, while in Mode II, shown in Fig. 6, the resonant voltage on capacitors and reaches zero after ac voltage changes direction. In Fig. 5, the solid-line and dotted-line waveforms of inductor current and capacitor voltages and illustrate the operation at maximum load and zero load, respectively. In Fig. 6, only the waveforms at maximum load are presented. Ini-

Fig. 4. (c) T (f) T

0T 0T

Topological stages: (a) [Mode II], (d) T [Mode II].

T 0 T , T 0 T [Mode I], (b) T 0 T , 0 T , T 0 T [Mode I], (e) T 0 T , and

and and (1)

tial values of inductor current and capacitor voltages in each topological stage are also shown in Fig. 4. During interval , Fig. 4(a), both switches, , are on and the inductor current linearly increases as

, switch turns off and a resonance starts between At and . The equivalent resonant circuit is shown in Fig. 4(b). This is a series resonant circuit with a capacitor-parallel load. The initial conditions are and (2)

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Fig. 5.

Key waveforms in Mode I. Fig. 6. Key waveforms in Mode II.

During the resonance, the inductor current and the capacitor voltage vary as [5] (3) and (4) where is de?ned as (5) (6) is the angular resonant frequency, and (7) is the characteristic impedance of the series resonant circuit in Fig. 4(b). Using the trigonometric angle-sum and angle-difference relationships, (3) and (4) can be rewritten as (8) and (9) (14) where (10) (11) and a (12) and (15) respectively, whereas, the resonant-capacitor voltage is equal to zero. Therefore, at , switch can be turned on with zero-voltage switching (ZVS). If , from until the end At the beginning and at the end of the resonant interval Fig. 5, the resonant-inductor current is determined as

Fig. 7. Relationship between V , V , Z

1I , and 1.

The relationship between , , , and , de?ned in (10) and (12) is also shown in Fig. 7. The sinusoidal waveforms of the inductor current and capacitor voltage determined in (8) and (9), respectively, can be easily recognized in Figs. 5 and 6 during interval . In Fig. 5, interval is the total resonant interval (13) in

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of the positive half switching cycle the inductor current linearly . increases with the same slope as during interval is only the ?rst part, , of the In Fig. 6, interval , the resonant-inductor curtotal resonant interval . At rent and resonant-capacitor voltage have the values (16) and (17) , ac voltage changes direction and respectively. At the topology of the equivalent resonant circuit changes from Fig. 4(b) and Fig. 4(c). As the topology in Fig. 4(c) differs from the topology in Fig. 4(b) only in the sign of the voltage source , the expressions for the inductor current and capacitor voltage during the second resonant interval in Fig. 6 can be easily obtained by rewriting (8) and (9) as (18) and (19) where (20) (21) and a At the end of the second resonant interval inductor current is determined as (22) , the resonant (23) whereas, the value of the resonant-capacitor voltage is zero, as , switch can be turned shown in Fig. 6. Therefore, at on with zero-voltage switching (ZVS). It should be noted in both , when switch turns off, the Fig. 5 and Fig. 6 that at switch current is equal to only , which means that the switch turns off with almost zero current switching (ZCS). During the negative half cycle of a switching period , the behavior of the circuit is the same as during the positive half cycle. The only difference is that switches and change roles. The total linear increase/decrease of the inductor current during a half switching cycle in both Figs. 5 and 6 is obtained as (24) and , i.e., It should be noted in Fig. 5 that if if the termination of the resonant interval coincides with the end of a half switching cycle, , because

and If, in Fig. 5, inductor current during intervals

, the linear change of the and is (26)

which follows from the half-wave symmetry of the inductor current waveform. Consequently

(27) as shown in Fig. 5. Finally, using the half-wave symmetry of the inductor current in Fig. 6 can be expressed as waveform, (28)

B. Output Voltage Regulation The output voltage regulation can be explained observing the waveforms in Fig. 5. The output voltage is equal to the average (or ) during a switching period voltage across capacitor

a

(29)

(25)

It follows from (29) that the regulation of output voltage versus load current variations, at a constant input voltage , can be achieved by keeping constant. Because 2, as de?ned in (5), with increasing , should also increase in constant. As illustrated in Fig. 5, the waveorder to keep form of the ac component of the inductor current, 2, which charges and discharges the resonant capacitor during the resonant interval is the same at and 0. Therefore, the corresponding waveforms of the resonant-capacitor voltage and 0 are identical and the output voltage is the at same at and 0. However, the waveforms of the inare phase shifted ductor current and capacitor voltage at compared to the corresponding waveforms at 0. In fact, with increasing load current the resonant interval is more phase shifted with respect to the beginning of a half switching cycle. Comparing the waveforms in Figs. 5 and 6, it can be seen in Fig. 6 is larger that the phase shift of the resonant interval than the maximum possible phase shift in Fig. 5. In fact, by extending the operation of the circuit from Mode I in Fig. 5 to Mode II in Fig. 6, an additional phase shift can be achieved, i.e., the operation range of the circuit can be extended to larger load currents without changing the values of the resonant inductance and resonant capacitance. Because of the two resonant intervals, the output voltage in Mode II cannot be expressed in a simple closed form such as (29) in Mode I. Nevertheless, the output voltage regulation in Mode II is similar to the output voltage regulation in Mode I. To facilitate the understanding of the output voltage regulation versus input voltage and load current variations in the whole

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The output voltage in operating point is obtained from (29) as

at

0 (31)

Finally, from (31), the resonant period can be determined as (32) Second, operating point ered. In operating point , at constraint can be de?ned: is consid, the following time (33) coinwhich means that the termination of resonant interval cides with the end of a half switching cycle. In this case, the total linear increase/decrease of the inductor current during a half switching cycle, , is equal to as explained in is determined as (25). Substituting (13) and (12) in (24), a (34)

Fig. 8.

V

= ( 1 ) characteristics.

f V ; I

output-voltage range from to , (29) which de?nes is graphed in Fig. 8 as a family of characwith used as a parameter. The four teristics , are also de?ned in Fig. 8. extreme operating points, From Fig. 8, the following relationships can be observed: , increases approximately linearly ? at with increasing ; slightly decreases ? the slope of characteristics with increasing ; , increases with increasing ; ? at , decreases with increasing ; ? at at and (operating point ); ? at and (operating point ). ? III. DESIGN After selecting the switching frequency , the key design parameters are the turns ratio of the transformer , the resonant inductance , and the resonant capacitance . Design constraints are de?ned in the four extreme operating points in Fig. 8. To use the characteristics in Fig. 8, ?rst the turns ratio of the transformer should be selected. After selecting the turns ratio of the transformer, resonant inductance and resonant capacitance can be obtained by considering the four extreme operating points in Fig. 8. First, operating point is considered. In operating point , the regulation parameter . It follows from Fig. 5 and (12) that must have a positive value, i.e., 0. In addition, it follows from Fig. 8 that a larger in operating point results in a larger in operating point . Obviously, a larger means larger rms values of the inductor current and switch current. Therefore, to obtain the smallest possible , the minimum value of the regulation parameter should be selected as (30) , increases to It should be noted in Fig. 5 that at , therefore, , and the inductor-current waveform during the resonant interval becomes a full sine wave, while the capacitor-voltage waveform becomes a full cosine wave.

in (34) has minimum in It can be proven analytically that . However, the same can be concluded with operating point the following simple reasoning. Because in operating point the input voltage is , the inductor current increases ; therefore, the inductor with a minimum slope equal to . current needs the longest time interval to increase by Further, along the vertical characteristic in Fig. 8, resonant interval has maximum value in operating point , as follows from (12) and (13). In fact, in operating point , has a minimum value, therefore, has a maximum value, resulting in a maximum value of . The longest time interval needed for the inductor current to increase by and the maximum resonant interval satisfy the constraint de?ned in (33). Substituting and in (34), it follows that in operating point a The product (35)

in (35) can be determined from (29), i.e., A

After substituting ductance is obtained as

(36) from (36) in (35), the resonant ina (37)

If the design includes Mode II in Fig. 6, then in (37) represents the maximum load current in Mode I in Fig. 5, which is, typically, 50%–75% of the total maximum load current. Finally, the resonant capacitance is determined directly from (32) and (37) as (38) Third, operating point is considered. It can be proven analytically that the switches in Fig. 3

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Fig. 9. Simpli?ed circuit diagram of a 1.8-MHz, 48-V, 65-W VRM module.

have maximum voltage stress in operating point . The voltage stress on the switches is determined by the peak value of the resonant-capacitor voltage, de?ned in Figs. 5 and 6 as (39) from (10) in (39), the maximum voltage stress Substituting on the switches is determined as (40) The maximum voltage stress on the switches determined by (40) is used for checking the proper selection of the turns ratio of the transformer. If the maximum voltage stress on the switches is smaller than the breakdown voltage of the switches with enough safety margin, it can be concluded that the turns ratio of the transformer was properly selected. IV. IMPLEMENTATION OF 1.8-MHz, 48-V VRM The 1.8-MHz, 48-V, 130-W VRM is implemented as two 65-W VRM modules connected in parallel. The current-source property of the VRM topology allows paralleling of two or more modules without special current-sharing precautions. The two VRM modules are implemented on the same printed circuit board (PCB). Each VRM module occupies half of the PCB area. A. 65-W VRM Module The simpli?ed circuit diagram of one 1.8-MHz, 48-V, 65-W VRM module is shown in Fig. 9. The input voltage range is 48 V 10 43.2 52.8 V. The output voltage range is 0.95–1.7 V. The maximum load current per VRM module is 50 A at 0.95–1.3-V output voltage range, while at 1.3–1.7-V output voltage range, the maximum load current is determined by the maximum output power of 65 W. The primary-side half-bridge inverter is implemented with FDS3672 (100 V, 7.5 A, 22 m ) MOSFETs from Fairchild. Each of the secondary-side synchronous recti?ers and is implemented with ?ve parallel IRF7811W (30 V, 14 A, 9 m ) MOSFETs from IR. Transformer is implemented with planar cores PC50ER14.5/6-Z from TDK and with helical windings. The turns ratio of the transformer is 5. The primary-side magnetizing and leakage inductance of the transformer is around 25 H and 90 nH, respectively. External resonant inductance is implemented with a toroidal core T37-2

Fig. 10. Functional block diagram of the control circuit.

Fig. 11. Key waveforms of the control circuit.

from Micrometals and nine turns, two strands of 0.6 wire. The inductance of is around 330 nH. Therefore, the total primary-side resonant inductance is around 420 nH. Output-?lter inductances and are coupled. They are implemented with two stacked planar EI cores 14/3.5/5 (3F3), with 1-mil air gap, and with single turn copper bars. The inductance of each and is around 80 nH. Finally, output-?lter capacitance is implemented with surface mount ceramic capacitors. The whole output-capacitance bank is arranged in a 3 8 matrix form. B. Control Circuit The functional block diagram of the control circuit is shown in Fig. 10. Key waveforms are presented in Fig. 11. The clock signal in Fig. 10 has a frequency equal to 3.6 MHz. The two D ?ip-?ops, DFF SR and DFF HB, operate as frequency dividers by 2. Therefore, the frequency of the SR and HB gate drive signals is equal to 1.8 MHz. The phase-shifted control is achieved by phase shifting the SR control pulses with respect to the HB control pulses. With increasing load current, error-ampli?er voltage increases and, through the comparator, the phase shift of the SR control pulses increases with respect to the HB control pulses.

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Fig. 12.

Resonant gate drive circuit.

Fig. 14. Key waveforms of the improved resonant gate-drive circuit obtained , (b) i , (c) v , and (d) v . by PSPICE simulation: (a) SR

Fig. 13.

Key waveforms of the resonant gate drive circuit.

C. Gate-Drive Circuit The HB gate drive signals are applied to the gates of the HB switches through a gate-drive transformer. The HB switches operate with partial ZVS switching. The SR gate drive signals are applied to the gates of the SRs through a resonant circuit. A resonant gate drive for the SRs at 1.8-MHz switching frequency is absolutely necessary because of the large input capacitance of the SR MOSFETs. The circuit diagram of the resonant gate drive for the SR’s is shown in Fig. 12. Transformer is implemented with planar cores PC50ER9.5/5-Z from TDK with 4-mil gap. The turns ratio of . The primary-side magnetizing inthe transformer is is around 2 H, while the leakage inductance is ductance around 220 nH. Key waveforms are presented in Fig. 13. The waveforms in Fig. 13 are obtained for the simpli?ed case when

0 and when the leakage inductance of is neglected. The basic operation of the resonant gate drive circuit in Fig. 12 is similar to the basic operation of the main resonant converter in Fig. 3. This can be concluded by comparing the waveforms of and resonant capacitor voltage the resonant inductor current in Fig. 13 with the corresponding waveforms in Fig. 5. It should be noted that the total resonant capacitance in Fig. 12 consists of capacitance and the gate-source capacitance of the SR re?ected to the primary side of the transformer. Bias ca, and diode in Fig. 12 form a peak pacitor , resistor detector circuit, which automatically provides a bias voltage for the SR. An improvement of the gate-drive voltage waveform can be achieved by adding inductor as shown in Fig. 12. By proper selection of inductance , a third harmonic can be injected in the gate-drive voltage waveform, which results in steeper edges and in an increased pulse width. Key waveforms of the improved resonant gate-drive circuit, obtained by PSPICE simulation, are presented in Fig. 14. It should be noted that the width of the SR gate-drive pulses is critical for the proper operation of the resonant VRM. The resonant gate drive circuit in Fig. 12 generates gate-drive pulses of a constant width. However, the optimal width of the gate drive pulses varies with both the input and output voltages, as follows from (12) and (13). Therefore, with the resonant gate drive circuit in Fig. 12, optimal gate drive pulses can be obtained only for a narrow range of input and output voltages. Otherwise, if the generated pulse width is greater than the optimal pulse width, the body diode of the SR will conduct; or, if the generated pulse width is smaller than the optimal pulse width, the SR will turn on with hard switching. In both cases, the ef?ciency of the VRM will be reduced. Finally, if the generated pulse width is insuf?cient, the resonant VRM will oscillate. In applications, where the reduction of the ef?ciency is not acceptable, instead of the RCD bias circuit in Fig. 12, a controlled bias circuit has to be employed. A possible solution to take into account the effect of the input voltage on the SR gate drive is to design the auxiliary voltage supply to be proportional to the input voltage. If is generated as an isolated nonregulated voltage supply operating in an open loop, will be proportional to the input voltage. The effect of the output voltage can be taken into

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Fig. 15. Operation of the resonant VRM at fast load-current transient from 75 to 100 A with 100-A=s slew rate, obtained by PSPICE simulation: i , (b) ramp (a) load current and output-?lter inductor current i and error-ampli?er voltage v , (c) resonant-capacitor voltage v voltage v , v , and (d) load voltage (Time scale: 1 s/div).

+

Fig. 16. Operation of the resonant VRM at slow load-current transient from 0 to 75 A with 10-A=s slew rate, obtained by PSPICE simulation: (a) load i , (b) ramp voltage current and output-?lter inductor current i and error-ampli?er voltage v , (c) resonant-capacitor voltage v , v v , and (d) load voltage (Time scale: 1 s/div).

+

account by a voltage-controlled voltage source connected in series with the secondary winding of the gate-drive transformer and controlled by the output voltage. D. Load-Current Transients Load-current transients are speci?ed as fast load-current transients 75–100 A and 100–75 A with a 100 A s slew rate, and as slow load-current transients 0–75 A and 75–0 A with a 10 A s slew rate. The key requirement during the load-current transients is the maximum deviation of the output voltage, which is speci?ed as 7% of the desired output voltage. The operation of the resonant VRM at fast and slow load-current transients is illustrated in Figs. 15 and 16, respectively. The waveforms in Figs. 15 and 16 are obtained by PSPICE simulation at the nominal input voltage of 48 V and the nominal output voltage of 1.3 V. The load includes 120- F decoupling capacitance on the microprocessor board. The connector between the VRM and the microprocessor board is modeled with 0.6-m resistance and 400-pH inductance connected in series. During the fast load-current transient from 75 to 100 A, shown in Fig. 15, the load voltage exhibits an initial drop, which is caused by the equivalent series inductance (ESL) and equivalent series resistance (ESR) of the decoupling capacitance on the microprocessor board. After the initial drop, the load voltage is determined by the discharging of the output ?lter capacitor because the output ?lter inductor current cannot follow the fast-increasing load current. The ramp-up of the output ?lter inductor current is mainly determined by the speed of the control loop. The closed loop bandwidth is around 125 kHz. As shown in Fig. 15, the rise time of the output ?lter inductor current is around ?ve–six clock periods. If the response of the inductor current to the step change of the load current is approximated as a second-order system with the oscillation frequency close to the control loop bandwidth, the rise time of the inductor current can be approximated as a quarter of the oscillation period [6], i.e., 1 4 2 s. It should be noted in Fig. 15 that during the ramp-up of the inductor current, the increased error-ampli?er voltage increases the phase shift of the SR control pulses with respect to the beginning of the

increases, and more energy is stored in the switching cycle, resonant inductor. As a result, larger resonant voltage pulses are and . Because generated across the resonant capacitors the average voltage across the resonant capacitors is now larger than the output voltage, the inductor current will increase. The recovery of the load voltage and the inductor current is determined by the bandwidth and the phase margin of the control loop. The phase margin of the closed loop is around 30 . The phase margin is relatively low because in high-frequency high-bandwidth converters even small delays of the control loop components contribute to the reduction of the phase margin [7]. During the slow load-current transient from 0 to 75 A, shown in Fig. 16, the effect of the ESL and ESR of the decoupling capacitance on the microprocessor board is negligible and the load voltage is mainly determined by the discharging of the output ?lter capacitor. As shown in Fig. 16, the output ?lter inductor current closely follows the slow increasing load current. However, because of the initial delay in the control loop, the inductor current slightly lags the load current, resulting in the discharging of the output ?lter capacitor. E. Over-Load Protection Typical VRM speci?cations require to shut down the converter in the case of an overload. The inherent current limiting feature of the resonant VRM (due to the series inductance) is very useful. In the case of an overload, the output voltage drops and the current limiting feature limits the instantaneous power delivered to the load at a level slightly higher than maximum power level of the converter. After that, an under-voltage protection mechanism shuts down the converter. V. EXPERIMENTAL RESULTS Ef?ciency measurements at nominal output voltage 1.3 V are shown in Fig. 17. These measurements were obtained before the output connector. The resistance of the output connector is 0.5–0.6 m . Therefore, the maximum power loss of the output connector is around 5–6 W. The ef?ciency at the nominal input voltage of 48 V, at 50–100 A load current is around

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Fig. 17.

Ef?ciency measurements at nominal output voltage V

= 1.3 V.

Fig. 19. Output voltage waveform at slow load-current transient (a) 0–75 A and (b) 75–0 A with 10-A=s slew rate (V 48 A, V 1.3 V).

=

=

voltage at fast and slow load-current transients is around 47 mV and 60 mV, respectively. These results satisfy the speci?cation requirement (7% of 1.3 V 91 mV) with a large margin. VI. CONCLUSION The main features of the new high-frequency resonant converter technology with phase-shifted regulation [3], [4] can be summarized as follows: ? simple isolated topology: half-bridge inverter + currentdoubler recti?er with synchronous recti?ers (SRs); ? topology suitable to utilize parasitics of components and layout; ? phase-shifted control with overlapping conduction of resonant SRs; ? resonant gate drive of resonant SRs; ? ZVS and partial ZCS of resonant SRs; ? only surface mount ceramic capacitors at the output; ? fast transient response; ? ef?ciency measured before the output connector around 82–84%; ? inherent current limit protection (due to series inductance); ? cost-effective. REFERENCES

[1] E. Stanford, “Intel VR technology roadmap,” in Proc. Intel Technology Symp., Sep. 2001, pp. 1.1–1.7. [2] M. Ye, P. Xu, B. Yang, and F. C. Lee, “Investigation of topology candidates for 48-V VRM,” in Proc. IEEE Applied Power Electronics Conf. (APEC), Mar. 2002, pp. 699–705.

Fig. 18. Output voltage waveform at fast load-current transient (a) 75–100 A and (b) 100–75 A with 100 A=s slew rate (V 48 V, V 1.3 V).

=

=

82%–84% before the output connector and around 80%–82% after the output connector. Transient-response measurements obtained at nominal input voltage of 48 V and nominal output voltage of 1.3 V are shown in Figs. 18 and 19. Fig. 18(a) and (b) show the output voltage waveforms at fast load-current transients 75–100 A and 100–75 A, respectively, with a 100-A s slew rate, while Fig. 19(a) and (b) show the output voltage waveforms at slow load-current transients 0–75 A and 75–0 A, respectively, with a 10-A s slew rate. The maximum deviation of the output

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[3] R. M. Porter, “High frequency conversion for powering microprocessors,” in Proc. HP GPST Power Supply Technology Symp., Oct. 2000, pp. 6.1–6.10. [4] G. G. Gurov, “System for Controlling the Delivery of Power to DC Computer Components Utilizing Phase Shift Regulation,” U.S. Patent 6 590 786 B2, Jul. 8, 2003. [5] N. Mohan, T. M. Underland, and W. P. Robbins, Power Electronics: Converters, Applications, and Design. New York: Wiley, 1995, pp. 255–256. [6] K. Yao, Y. Ren, and F. C. Lee, “Critical bandwidth for load transient response of voltage regulator modules,” IEEE Trans. Power Electron., vol. 19, no. 6, pp. 1454–1461, Nov. 2004. [7] L. Ma and A. Q. Huang, “Impact of time delay and error ampli?er parameters to high-bandwidth voltage regulator module (VRM) controller design,” in Proc. CPES Power Electronics Sem., Apr. 2004, pp. 230–235.

? Milan M. Jovanovic (F’01) was born in Belgrade, Serbia. He received the Dipl.Ing. degree in electrical engineering from the University of Belgrade, Serbia. Presently, he is the Chief Technology Of?cer (CTO) of the Power Systems Business Group, Delta Electronics, Inc., Taipei, Taiwan, R.O.C.

Laszlo Huber (M’86) was born in Novi Sad, Yugoslavia, in 1953. He received the Dipl.Eng. degree from the University of Novi Sad, Novi Sad, in 1977, the M.S. degree from the University of Niˇ, s Niˇ, Yugoslavia, in 1983, and the Ph.D. degree from s the University of Novi Sad, in 1992, all in electrical engineering. From 1977 to 1992, he was an Instructor at the Institute for Power and Electronics, University of Novi Sad. In 1992, he joined the Virginia Power Electronics Center, Virginia Polytechnic Institute and State University, Blacksburg, as a Visiting Professor. From 1993 to 1994, he was a Research Scientist at the Virginia Power Electronics Center. Since 1994, he has been a Senior Member of the R&D Staff at the Power Electronics Laboratory, Delta Products Corporation, Research Triangle Park, NC, the Advanced R&D Unit of Delta Electronics, Inc., Taipei, Taiwan, R.O.C. (one of the world’s largest manufacturers of power supplies). His 28-year experience includes the analysis, simulation, and design of high-frequency, high-power-density, single-phase, and three-phase power processors; modeling, simulation, evaluation, and application of high-power semiconductor devices; and modeling, simulation, analysis, and design of analog and digital electronics circuits. He has published over 70 technical papers and holds four U.S. patents.

Dennis J. Solley received the Ph.D. degree from King’s College, University of Cambridge, Cambridge, U.K., in 1970. His dissertation was on the observation and interaction of magnetic domain walls with nonmagnetic inclusions in nickel silicon crystals using transmission and scanning electron microscopy. He has spent 30 years in power electronics working in England, Canada, and the United States of America, most recently at Advanced Energy, IKOR, Fort Collins, CO, in the high-end server market segment.

Gennady Gurov received the M.Eng. degree in radio-engineering from the Institute for Radio-Techniques, Electronics, and Automatics, Moscow, Russia, in 1972 and the Ph.D. degree in particle accelerators from the Institute for High Energy Physics, Protvino, Russia, in 1980. Since 1996, he has been with Advanced Energy Industries, Inc., Fort Collins, CO. His activities concern essentially power electronics.

Kevin Hsu was born in Taoyuan, Taiwan, R.O.C., in 1974. He received the A.E. degree from the Junior College of St. John & St. Mary Institute of Technology, Taipei, Taiwan, in 1994 and the Dipl.Eng. degree from the University of Chung-Yuan, Chungli, Taiwan, in 1997, all in electrical engineering. Since 1996, he has been an Electrical Design Engineer at the dc/dc and Networking Business Unit, Power Supply Business Group, Delta Electronics, Inc., Taoyuan Shien (one of the world’s largest manufacturers of power supplies). His experience includes the design of standard power supplies for desktop computers, design of high-power-density power supplies for networking and telecom systems, design of high-current-density and low-pro?le VRMs, design of high-power and multiple-outputs adaptors; evaluation and application of power semiconductor devices; and design of analog electronics circuits.

Robert M. Porter received the B.S. degree in electrical engineering with emphasis in semiconductor physics from the University of Florida, Gainesville, in 1972. He worked eleven years for Delco Electronics (a division of General Motors) in power transistor and power IC development and power transistor applications. The following six years, he worked on highpower short-wave transmitter design at two companies. Since 1990, he has been with Advanced Energy (AE), Fort Collins, CO, where his two previous careers came together with solid-state high-frequency high-power design. He was a substantial design contributor to a substantial piece of the RF business at AE and in recognition in 1997 he was named Technical Fellow (one of three such positions at AE). For the last ?ve years, he has been with IKOR (a new business unit at AE) where he is currently the Vice President of Engineering. This group is focused on providing low output inductance solutions for powering microprocessors.